# BARE PCB TESTS QUESTION

Enrico
Guest
Posts: n/a

 06-20-2011, 04:26 PM
Hi,

I'm trying to understand how bare PCB's are tested and the differences
between SMD and PTH tests.

I heard of:

1) FIXTURE

2) SMD TEST

3) DOUBLE SMD TEST

4) PTH TEST

5) FLYING PROBE

-------------------------------------------------------------------------------------------------------------------------------
I also wanted to know if the following point is correct:

Let's say I have to route a net which connects 5 PADS.
If I route the net in a way where PADS 1 and 5 are the only terminal
points:

1 -- 2 -- 3 -- 4 -- 5

The PCB tracks pass through PADS 2, 3, AND 4.

If I understand correctly, I need only 2 probes to test this net,
right?

Do I save money when testing the PCB?

Thanks,
Enrico Migliore

Don Y
Guest
Posts: n/a

 06-20-2011, 04:51 PM
On 6/20/2011 9:26 AM, Enrico wrote:
> Hi,
>
> I'm trying to understand how bare PCB's are tested and the differences
> between SMD and PTH tests.
>
> I heard of:
> 1) FIXTURE
> 2) SMD TEST
> 3) DOUBLE SMD TEST
> 4) PTH TEST
> 5) FLYING PROBE
>
> -------------------------------------------------------------------------------------------------------------------------------
> I also wanted to know if the following point is correct:
>
> Let's say I have to route a net which connects 5 PADS.
> If I route the net in a way where PADS 1 and 5 are the only terminal
> points:
>
> 1 -- 2 -- 3 -- 4 -- 5
>
> The PCB tracks pass through PADS 2, 3, AND 4.
>
> If I understand correctly, I need only 2 probes to test this net,
> right?

Depends on what your test wants to "prove". Assuming no
gross errors in the artwork(s), your test will verify
*continuity* but nothing more. E.g., a "whisker" that
shorts this net to some *other* net proximate to the
routing of this net will be undetected.

> Do I save money when testing the PCB?

Are you likely to encounter failures in the bare boards?
Or, are you more likely to encounter failures in the
*assembled* boards. (hint: take door number 2!!)

Enrico
Guest
Posts: n/a

 06-20-2011, 05:01 PM
Hi,

> *E.g., a "whisker" that
> shorts this net to some *other* net proximate to the
> routing of this net will be undetected.

Could you be more specific, please?

Thank you,
Enrico Migliore

Don Y
Guest
Posts: n/a

 06-20-2011, 05:29 PM
On 6/20/2011 10:01 AM, Enrico wrote:
> Hi,
>
>
>> E.g., a "whisker" that
>> shorts this net to some *other* net proximate to the
>> routing of this net will be undetected.

>
> Could you be more specific, please?

Imagine a netlist:
U1(1) - U5(3) - U19(2) ... U17(6)

(we don't care if it is linear or forked)

Imagine another netlist:
U1(2) - U8(12) - U6(5) ...

Now, imagine between pins 1 & 2 on U1, there is a tiny
bit of foil (that wasn't completely etched away) that
bridges the annular rings between these two pins. I.e.,
AS IF pins 1 & 2 were *shorted* together.

If all you are interested in is verifying continuity
between the pins *in* a net (i.e., U1(1) *does* connect
to U5(3) which *does* connect to U19(2) ... ), then
you won't see the short to pin U1(2).

When we've tested bare boards on bed of nail testers,
we always looked for continuity *and* isolation -- a
"whisker" is just as bad as an "open foil".

[though I question your need to test bare boards at
all... look at your artwork and process, first, to
decide if this is going to give you any real value
for the money spent. A better board house may be

Steve at fivetrees
Guest
Posts: n/a

 07-06-2011, 09:32 PM
On 20/06/2011 18:29, Don Y wrote:
> [though I question your need to test bare boards at
> all... look at your artwork and process, first, to
> decide if this is going to give you any real value
> for the money spent. A better board house may be

Some years ago (early 80s) the company I worked at did an analysis of
faults found and the costs involved in fixing them. It's fairly well
known that, for every stage of the manufacturing process a board goes
through, fault rectification costs increase by an order of magnitude. We
made a point of ordering BBT (bare-board test) on every PCB thereafter.
It was cheap insurance. To be fair, we had recently been hit by a series
of etching faults, the likes of which I don't see these days...

That was back in the days of double-sided boards. Nowadays, with 6- or
8-layer boards, I still do order BBT (it's still cheap). I'd hate to
have several hundred pounds-worth of components scrapped due to an
etching fault I can't fix.

To the OP: more recently (but still about 15 years ago, IIRC) I
redesigned a bare-board tester for a client. There are various
strategies, and the best work in the analogue domain and measure e.g.
resistance. This system worked in the digital domain: basic idea was
that every pad was probed (bed of nails), and the system typically
learned a netlist from a known-good new board by driving each node high
(5V), and recording all other nodes that lit up and so formed a net.
(There was a bit more to it than that, but hey.) Testing was done by
repeating this process, comparing the netlists, and (intelligently -
took a while to perfect) reporting any differences, whether due to
shorts or opens.

Testing time increased as the square of the number of nets. The reason
for this is left as an exercise for the reader .

Steve

--
http://www.fivetrees.com

Don Y
Guest
Posts: n/a

 07-07-2011, 01:47 AM
Hi Steve,

On 7/6/2011 2:32 PM, Steve at fivetrees wrote:
> On 20/06/2011 18:29, Don Y wrote:
>> [though I question your need to test bare boards at
>> all... look at your artwork and process, first, to
>> decide if this is going to give you any real value
>> for the money spent. A better board house may be

>
> Some years ago (early 80s) the company I worked at did an analysis of
> faults found and the costs involved in fixing them. It's fairly well
> known that, for every stage of the manufacturing process a board goes
> through, fault rectification costs increase by an order of magnitude. We

The same applies to software development... :> Amusing how few
firms actually address it with the same sense of "rationality"!
(i.e., spec, code, test, test, test, test, test, release)

> made a point of ordering BBT (bare-board test) on every PCB thereafter.
> It was cheap insurance. To be fair, we had recently been hit by a series
> of etching faults, the likes of which I don't see these days...
>
> That was back in the days of double-sided boards. Nowadays, with 6- or
> 8-layer boards, I still do order BBT (it's still cheap). I'd hate to
> have several hundred pounds-worth of components scrapped due to an
> etching fault I can't fix.

I haven't seen a problem that wasn't caught by examining the
"test coupons" alongside the board (checking buried vias, etc.)
The worst problems I've seen were from stuffig the wrong parts
XXX and XXx are "interchangeable" parts -- when, of course, they
weren't!)

> To the OP: more recently (but still about 15 years ago, IIRC) I
> redesigned a bare-board tester for a client. There are various
> strategies, and the best work in the analogue domain and measure e.g.
> resistance. This system worked in the digital domain: basic idea was
> that every pad was probed (bed of nails), and the system typically
> learned a netlist from a known-good new board by driving each node high
> (5V), and recording all other nodes that lit up and so formed a net.
> (There was a bit more to it than that, but hey.) Testing was done by
> repeating this process, comparing the netlists, and (intelligently -
> took a while to perfect) reporting any differences, whether due to
> shorts or opens.

This only catches gross errors. And, at "DC". Things like *sizable*
whiskers or gaps. I.e., a bad annular ring won't turn up until the
board is assembled, flexed, powered, etc.

> Testing time increased as the square of the number of nets. The reason
> for this is left as an exercise for the reader .

The other dirty little secret is that it requires a lot of time to
SET UP the test in the first place (i.e., what point in the
circuit does pogo pin #87 correspond with?). And, interpreting
the results -- "OK, there's a short between Net 457 and 1933 -- now
*where* is it? Is it a whisker on an internal plane, etc.?"
(since you usually want to *see* the problem to verify it -- or,
has a pogo pin been bent a bit so that *it* is now shorting to
that other net when the clamshell is closed...)

I think the OP is best advised to look at his total process
and see where problems are likely to come in -- unless budget
is not an issue and you can opt for the peace of mind of a
"belts and braces" approach! :>

colin_toogood@yahoo.com
Guest
Posts: n/a

 07-07-2011, 01:34 PM
On Jul 6, 10:32*pm, Steve at fivetrees <(E-Mail Removed)>
wrote:
> On 20/06/2011 18:29, Don Y wrote:
>
> > [though I question your need to test bare boards at
> > all... look at your artwork and process, first, to
> > decide if this is going to give you any real value
> > for the money spent. *A better board house may be

>
> Some years ago (early 80s) the company I worked at did an analysis of
> faults found and the costs involved in fixing them. It's fairly well
> known that, for every stage of the manufacturing process a board goes
> through, fault rectification costs increase by an order of magnitude. We
> made a point of ordering BBT (bare-board test) on every PCB thereafter.
> It was cheap insurance. To be fair, we had recently been hit by a series
> of etching faults, the likes of which I don't see these days...
>
> That was back in the days of double-sided boards. Nowadays, with 6- or
> 8-layer boards, I still do order BBT (it's still cheap). I'd hate to
> have several hundred pounds-worth of components scrapped due to an
> etching fault I can't fix.
>
> To the OP: more recently (but still about 15 years ago, IIRC) I
> redesigned a bare-board tester for a client. There are various
> strategies, and the best work in the analogue domain and measure e.g.
> resistance. This system worked in the digital domain: basic idea was
> that every pad was probed (bed of nails), and the system typically
> learned a netlist from a known-good new board by driving each node high
> (5V), and recording all other nodes that lit up and so formed a net.
> (There was a bit more to it than that, but hey.) Testing was done by
> repeating this process, comparing the netlists, and (intelligently -
> took a while to perfect) reporting any differences, whether due to
> shorts or opens.
>
> Testing time increased as the square of the number of nets. The reason
> for this is left as an exercise for the reader .
>
> Steve
>
> --http://www.fivetrees.com

Are you aware of the algorithms that JTAG test software uses. It
doesn't matter how many nets you have, the shorts and open test is
done in about 20 passes. I forget the name of the mathematical
algorithm used.

Colin

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