Cache mapping

Hi all

I have a machine with a cacheline size of 64 bytes and the cache has
an associativity of 8. That means that
each set is 512 bytes and as I have 32KB in total I have 64 different
sets. How I wonder how on a Dual core processor a physical address is
mapped to such a set. In other words, which bits of the physical
address determine the segment out of the 64 different ones into which
it maps. I was looking for ages on the web, but couldnt really find
any useful information. One assumptions of mine would be that its bit
[11..6]

Thanks!