Memory Mapping & Address Decoders

plzz would you answer this question

http://groups.google.co.uk/group/alt...41ee17de?hl=en

thx 8-)

wrote:
>
> plzz would you answer this question
> >Http://groups.google.co.uk/group/alt...41ee17de?hl=en

The I/O address space is separate from memory space.

You can have the same I/O and memory address exist without conflicting
with each other because a different CPU instruction is used to access
the I/O space.

The I/O space goes from 0 to 65535 (ie 64k). Memory goes from 0 to
maybe 1 gb and more (depending on the CPU and motherboard).

Thx Coputer Guy ... that's right and i'm okay with that issue ... but i
think both the RAM and ROM use the same address space (memory mapped
i/o) ... but i can't manage to understand how to control the RAM and
ROM sharing of these addresses ... is there a certain I/O port to
communicate with to enable or desable the logic of address detection
.... umm ... dono

<> wrote in message
news: ups.com...
> Thx Coputer Guy ... that's right and i'm okay with that issue ... but i
> think both the RAM and ROM use the same address space (memory mapped
> i/o) ... but i can't manage to understand how to control the RAM and
> ROM sharing of these addresses ... is there a certain I/O port to
> communicate with to enable or desable the logic of address detection
> ... umm ... dono

Why would you need that at first place?

Alex

wrote in news:1141940929.337294.11790
@j52g2000cwj.googlegroups.com:

> Thx Coputer Guy ... that's right and i'm okay with that issue ... but i
> think both the RAM and ROM use the same address space (memory mapped
> i/o) ... but i can't manage to understand how to control the RAM and
> ROM sharing of these addresses ... is there a certain I/O port to
> communicate with to enable or desable the logic of address detection
> ... umm ... dono
>

ROMS are memory devices and share the same address space with the
System RAM. I'm not up to speed any more on how memory management
works in a modern PC. But generaly speeking, the address decoder
looks at the address for a particular memory cycle and determines
if the RAM or the ROM should respond, then it generated the apropriat
chip select.

Hi,

wrote:
> Thx Coputer Guy ... that's right and i'm okay with that issue ... but i
> think both the RAM and ROM use the same address space (memory mapped
> i/o) ... but i can't manage to understand how to control the RAM and
> ROM sharing of these addresses ... is there a certain I/O port to
> communicate with to enable or desable the logic of address detection
> ... umm ... dono

For most PCI chipsets, in the PCI configuration space for the "PCI host
controller", there's settings that control what happens to accesses
to/from the area between 0x000C0000 and 0x000FFFFF (usually in banks of
16 KB or 32 KB).

Using the chipset you would be able to set these banks to "read only",
"write only", "read/write" or "not present" (for example).

During boot the system BIOS is actually just below 4 GB. When it starts
it sets it's area below 1 MB to "write only", then copies itself into
RAM, and then sets the area to "read only".

For the primary video card's display memory, sometimes the BIOS can set
the area from 0x000A0000 to 0x000BFFFF to "not present", which causes
accesses in this range to bypass RAM and go to the PCI bus instead, but
more often the chipset assumes this and doesn't allow the area to be
changed (and doesn't have a setting for it). I guess I should also
point out that most BIOS's use the RAM underneath the video display
memory for an SMM state save area (or for power management).

For a PCI device's ROM (e.g. the primary video card's ROM at
0x000C0000), the BIOS would set the relevant banks to "write only", so
that reads go to the PCI bus and writes go to RAM. Then it would copy
from the ROM (on the PCI bus) to RAM, by writing to the same addresses
that it reads the ROM data from. Once this is done the BIOS can change
these RAM banks to "read only", which is where your video BIOS shadow
comes from. Alternatively, the BIOS could set these areas to to "write
only" or "not present" so that reads get forwarded to the PCI bus
(shadowing is disabled).

For Intel chipsets, the registers that control all of this are in the
host controller's PCI configuration space (i.e. bus 0, device 0,
function 0) and are called the PAM registers (Programmable Attribute
Map registers). For the i440FX chipset they are at offsets 0x0059 to
0x005F. For Intel 845 and 865 chipsets the PAM registers are at offsets
0x0090 to 0x0096.

Now that you know this, don't touch any of it. :-)


Cheers,

Brendan

Thxxxxx Brendan .... that was really extra ordinary answer ... exactly
what i needed ... and thx also for all the other guyzzzzzzzz

just to end up me concerns now ... i conclude from what u've said that
(maybe i'm totally wrong):

1) on non-pnp-isa system, there were no such management so instead
there were fized holes in the memory space (e.g. between C0000-FFFFF)
.... and that means when shadowing on these systems, the shadowed RAM
address space can't be the same of the orinignal /O-memory adress space
(coz no read-/write-only/...etc management is present) ... am i right ?

2) on pnp-systems (pnp-isa and pci systems) ... it is just the way you
have said it however for back compatiblity the holes still present in
the address space ... is that right too ?

well Brendan ... my last concern really if u don't mind ... do u have
an msn/yahoo/skybe messenger account so i can add u to my list (don't
worry it is not all about computerz) 8-)

Thxxxxxx again