Percival P. Cassidy wrote:
> Paul wrote:
>
>>> I have two sticks of Kingston KVR400X72C3A/512 in my A8N-E. I don't
>>> recall whether I bought them as a matched pair or whether they were
>>> two individually packaged modules -- it's been a few years.
>>>
>>> Today for the first time I ran the CPU-Z utility and found that,
>>> although the SPD of one of these RAM modules shows an RAS# to CAS#
>>> delay of 3 for both 166MHz and 200MHz, the other's SPD indicates RAS#
>>> to CAS# delays of 11 and 13 respectively.
>>>
>>> The 1GB modules both show the RAS# to CAS# delay to be 3 -- the same
>>> as the first of the 512MB modules.
>>>
>>> Also, with the RAM speed set in the BIOS to Auto, the memory is being
>>> run at 333MHz. Why not 400MHz? I've just set it manually to 400MHz
>>> with a CAS# latency of 3.0 and tRAS of 8 (both as indicated by the
>>> SPD on all the modules), but which setting is really better?
>
>> The BIOS down-clocks the memory, as a function of the bus loading.
>>
>> AMD provided some tables long ago, showing what they thought the
>> processor memory controller could handle. And for two double sided
>> sticks per channel, they recommended DDR333 instead of DDR400.
>>
>> A user can certainly experiment with their own settings, doing
>> stability testing with memtest86+ and Prime95, then decide how well
>> their particular processor is doing. The conservative Auto settings,
>> help ensure the motherboard starts up OK.
>>
>> For example, these are some setting options, and where they
>> might be used.
>>
>> DDR400, Command Rate 1T One stick per channel of DDR400 (two
>> sticks total)
>>
>> DDR400, Command Rate 2T Two sticks per channel of DDR400 (four
>> sticks total)
>> DDR333, Command Rate 1T Two sticks per channel of DDR400 (four
>> sticks total)
>>
>> DDR333, Command Rate 2T A really conservative setting...
>>
>> The difference between DDR400 and DDR333, makes about the same
>> amount of difference, as changing between Command Rate 1T and
>> Command Rate 2T. Of the two options shown in the second
>> group above, the DDR400-2T beats the DDR333-1T by a small bit, so
>> is the one you can try first. (Somebody benchmarked it for us,
>> and that is how I found out.)
>>
>> "Command Rate" is a setting that affects how the Address/Command bus
>> works. The DIMM has two busses. The Address/Command handles
>> the requests, the Data bus handles the data. A "Command Rate" setting
>> of 2T, means the information on that bus is presented for two cycles,
>> and strobed during the second cycle. It cuts the bandwidth of
>> the Address/Command bus in half. Since the Address/Command bus
>> is not totally saturated, the impact is not a halving of
>> overall performance.
>>
>> Some motherboards have a Command Rate setting, staring you in the
>> face. But not all of them do. My Nforce2 motherboard, for example,
>> requires me to flash upgrade to a different BIOS code module,
>> to get 1T versus 2T operation (1T is the Asus default). So some
>> motherboard owners have a degree of inconvenience, to select
>> between the options. And apparently, some designs don't even
>> offer an option, and how it works is fixed by the hardware.
>> In that case, the chipset designer has figured it all out
>> for you.
>
>
> OK, but what about those weird SPD values for the second 512MB module?
>
> Perce
You can dump the SPD tables, with CPUZ. Go to the "About" tab,
and there is an option to save a report. Look for "Memory SPD"
in the text file.
http://www.cpuid.com/cpuz.php
There is a 256 byte table just below that. That should be a copy
of the serial EEPROM on the DIMM. One of the bytes, declares how
much of the table contains valid data. The rest of the contents,
you need a JEDEC document to decode the results.
You can start by comparing the tables for the presumed identical
DIMMs, and see if they look alike or not.
I can't remember right off hand now, whether SPD is protected
by a checksum or not.
It is too bad the JEDEC site is not that easy to search (or to
download from). I've located the "secret decoder ring" file
for a couple of memory technogies, from jedec.org, but it
is an annoying process.
The interesting part, from my perspective, is whether the
BIOS is paying attention to the erroneous SPD info or not.
Normally, a BIOS should respect the "slowest" DIMM, and set
the timing to suit that DIMM (so they all can work). If the
timing is not being influenced by the garbage data, then
perhaps the BIOS knows it isn't a valid table.
In terms of module sizing, the BIOS has a fallback algorithm,
where it tests for the "end" of each module, during POST.
So even if an SPD claims a DIMM is 1GB, and the module only
has 512MB, the BIOS can figure out the module is a 512. It
won't crash in that case. But I'm not aware of any way to
"fudge" timing. If the timing table is corrupt, you'd think
the BIOS would be forced to ignore the module entirely.
Paul
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