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Re: Mixing logic families design rules

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      12-09-2004, 04:19 AM
On Wed, 08 Dec 2004 19:57:26 +0000, Dave Boland wrote:

> I need to design a card that has a 3.3 volt processor on it, a couple of
> 5 volt CMOS parts, and interface to TTL. This is turning into a
> headache, so I'd appreciate some advice from experienced system/logic
> designers. Let me start by telling you what I think I know, and you can
> correct me.
> The processor is called 5 volt tolerant, which seems to mean it will
> handle a 5.1 volt input without problem. One reference I read said to
> add a 100 ohm resistor in series to limit current for the protection
> diodes in the processor.

I wouldn't use the 100 Ohm resistor. If the inputs have simple protection
diodes to their own VCC, then the chip is NOT 5 Volt tolerant.

> Right so far? What is the impact to
> reliability of the processor? The reason for asking about reliability
> is that I want a design that will work for years and years, not just
> long enough for a show and tell.

The datasheet for the processor will certainly list the absolute maximum
Voltages which may be applied to the input as well as recommended
operating conditions. If it says you can apply 5 Volts to the input pins,
then you don't need to do anything else.

> Back to that processor. The Voh is at least 2.5 volts and the Vol is
> about .5 volts, so the output looks like it would work with TTL. Right
> so far?

Sounds good.

> The processor outputs can be either totempole, or open drain. With open
> drain, I can pull it high so the output will be above the 3.5 volts
> needed by 5 volt CMOS. I assume (yes, I know what that word means) that
> the processor can pull the line to .6 volts or less for a low output.
> Will this work well and reliably?

I'm not sure. It isn't always safe to pull even open collector
outputs higher than VCC. But in this case, it kind of sounds as
though they are deliberately giving you the open collector outputs
so you can pull up to whatever level you need. You'll have to read
the datasheet. Also, you'll have to check how much current the outputs
can sink when they try to go low, as another poster said.

I'm trying to remember a similar problem I had. I think I had to
design an input that could be driven by either TTL or LVTTL, but the
chip was CMOS. So I put a tri-stateable 5 Volt TTL buffer in front of the
CMOS with a pullup on the output. Then I tied the disable to the input.
So when the input is high, the output is tri-stated, and the pullups
set the signal level. When the input is low, output is actively driven
low to TTL levels. But I was not concerned about propagation delay.

> I'm told that doing things as described will work, but I sacrifice
> propagation speed. Typical numbers seem to be 40 to 80 nS. This may be
> a problem for use on a bus.

I don't think this will be a problem for I2C. How fast is the bus?

> The alternative is an alphabet soup of logic families from ABT(?), HC,
> HCT, and others. This is where I feel especially in the dark. Any good
> rules of thumb for mixing logic families? I have some info from Philips
> (AN240 I believe), but is is almost 10 years old and fails to mention
> some of the logic families I see being used. Have also looked at other
> web sites, but things still seem as clear as mud.
> Finally, one particular troubling area is interfacing the I2C bus. It
> will see a 3.3 volt device, two 5 volt CMOS devices, and one TTL. Since
> this is a bidirectional bus things really get messy. Max has some
> devices to do this, but I don't know how well they work, or if there is
> a better alternative?

Well, you'll have to settle on a signalling standard for the bus.
Unfortunately, I think it is up to you to determine which one will cause
the least pain. ;-)

> Sorry for the long append. Hope no one dozes off reading this. Thanks
> for any helpful information.
> Dave,


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