(Arnold Z.) wrote in message news:<vNt2b.264949$> ...
> Hi all,
>
> I need to prototype some ASIC designs and I'm looking for
> advice on type of FPGA and on FPGA board as well (to buy one
> or alternatively to make one on my own).
>
> The FPGA should be capable of the equivalent of about 100K
> to 500K ASIC logic gates (being 300K a good estimate).
> But this is the least important point, since every family of
> FPGAs comes in various gate counts.
> What I really care most is to choose the right FPGA family
> since the start.
>
> Clock speed is not critically important, but it should not
> be lower than 50 MHz anyway.
>
> I'd like to match the FPGA design to the ASIC one as closely
> as possible, so I'm ruling out any FPGA that for its performance
> depends too much on some "original features".
> Sure, I don't pretend a FPGA with only 2-inputs NAND gates per
> cell and millions of freely routable cells.. but something as
> close as possible to an ASIC, because it will all end up on a
> ASIC anyway sooner or later, and I don't want the FPGA and the
> ASIC to be too much different each other, so to force me to
> find completely different solutions. I can sacrifice FPGA speed,
> but not to an extreme point. Hence, I'm looking for the most
> "ASIC-like" FPGA.
>
> In the past year I've written a program to simulate logic
> circuits (including the propagation delays associated with
> them). I'd like to continue the development with it (basically
> I will end up with a giant schematic full of NANDs, although
> I really use macros a lot, and absorb and encapsulate into them
> the various functional units, for increased simulation speed
> and to not get my mind blown).
> So I'd like to get documentation to program the FPGA chip by
> myself.. I don't mean just hardware wise, but also how to make
> a configuration bitstream out of a design, the exact timing
> constraints given by the routing, how to route, etc.. and the
> device should be as much "simple" as possible, so to not force
> me to think too much in a FPGA specific way, too much different
> from the future ASIC implementation. I just want a test bench
> for a future set of ASICs, running at a reasonable speed (i.e.
> anyway much faster than a PC simulation, although not full ASIC
> speed, of course, and probably not even one tenth of it).
> So FPGAs that are "too fancy" should be ruled out. I rather need
> something simple, to not be forced to think too much in terms
> of FPGA, but rather in future ASIC terms.
> Of course, even the most "ASIC like" FPGA out there will still
> be much different than an ASIC.. so I'm ready to rebuild my set
> of "macros" for that FPGA too.. to optimize them for that FPGA..
> as long as it's not too complex to do it (i.e. fancy FPGA design),
> and expecially the routing uses some clear rules, without weird
> exceptions, and is well documented propagation delay wise, etc..
> What I fear most is that it won't be possible to just place
> anywhere on the FPGA grid for example an adder, once I designed
> it for that specific FPGA (i.e. some complex routing rules and
> maybe annoying location constraints, which I'd really like to
> avoid).
>
> Now the sad part: I am on very low budget. This is a hobbyst
> project for me, but I think I have a very innovative and valid
> design in mind. I do not want to be ripped off, so I want to try
> it myself. I will enjoy doing so anyway, and time is not a big
> problem (I have some free time to invest on it). I have no
> digital electronics degree, although I'd say I'm very, very
> experienced assembly programmer (various 8..64 bit CPU's, DSPs
> and microcontrollers) and with a long experience in digital
> electronics as a self taught hobbist (no previous FPGA direct
> experience though!).
> As I said I've some rather interesting/innovative/original
> design/concept to develop and test, and the only viable way
> will be a FPGA. But which one? You certainly know much better
> than me!
>
> Once the design, on the FPGA, should prove its validity, I'd
> move on to look for investors and some ASIC engineer for the
> real thing.
>
> Your advice is sincerely extremely appreciated.
>
> Kindest regards,
> Arnold
This is why high-level languages like VHDL and Verilog are used.
If you describe your design in HDL, you don't care about the exact
logic used to implement it. If your design doesn't include FPGA-
specific constructs, it will be possible to port it to an ASIC.
Usually, the only device-specific part you must use will be
memories - if you use fully-synchronous memories you will probably
be OK.
In general, designing in HDL for FPGA is not very different from
designing for ASIC. The two main differences are: usually you need
more pipeline stages in FPGA, since the logic is slower; OTOH, you
need lower level of verification, since fixing bugs is much easier
and cheaper; there is no need to wait for a new chip - fixing a bug
takes hours instead of weeks or months.
Writing the design and verifying it for functionality are usually
the easiest part. Synthesizing and placing it is much more effort,
unless your design is slow and small relative to your target chip.
Sadly, synthesis, place and route are VERY device-dependent. Even
more sadly, there is no cook-book - it is a combination of experience
and trial-and-error process.
At the bottom line: why go to ASIC at all? developing ASICs is
incredibly expensive, way beyond the reach of most hobbyists
(unless you happen to be Bill Gates?) and FPGAs are cheap; the
unit-count where ASICs become cheaper than FPGAs is high and
getting higher all the time.
Linear Mode
