SPI Configuration

Hello,

I am trying to interface an MPC5554 procesor with 68HC908 processor
using SPI ( Serial Peripheral interface). MPC5554 is the Master CPU. I
have little experience in configuring the SPI in low level. I would like to
know the following.

1. What are the factors that I should consider while selecting the Clock
Polarity and Clock Phase? In my case both Master and Slave CPUs support
Clock Phase and Clock polarity of 0 and 1.

2. What are the factors that I should consider while deciding the delay
between the slave select signal and the first clock edge also the delay
between the last clock edge and the slave deselection?
i.e. The delay between Slave select going low and the first clock edge.

3. What should be the optimum time difference between the transmition of two
message frames?

It will be very helpful if somebody can throw some light on this.

Thanks and Regards,
Sreeram.

In-Line...
"Sreeram S" <> wrote in message news:dj0ioc$gjk$...
> Hello,
>
> I am trying to interface an MPC5554 procesor with 68HC908 processor
> using SPI ( Serial Peripheral interface). MPC5554 is the Master CPU. I
> have little experience in configuring the SPI in low level. I would like to
> know the following.
>
> 1. What are the factors that I should consider while selecting the Clock
> Polarity and Clock Phase? In my case both Master and Slave CPUs support
> Clock Phase and Clock polarity of 0 and 1.
>
I see most devices clock data in on the falling edge, although some are on the rising edge.

> 2. What are the factors that I should consider while deciding the delay
> between the slave select signal and the first clock edge also the delay
> between the last clock edge and the slave deselection?
> i.e. The delay between Slave select going low and the first clock edge.
>
This is meerly a setup time for the internal gates, a safe bet is 1/2 clock cycle.

> 3. What should be the optimum time difference between the transmition of two
> message frames?
>
Not sure what you mean, the data rate is based on the clock, so skewing of clock and data makes no difference to the slave.

> It will be very helpful if somebody can throw some light on this.
>
> Thanks and Regards,
> Sreeram.
>
>

Try reading datasheet from Microchip, they cover SPI buses quite
extensively with comprehesive diagram. The SPI bus serial data need to
settle HIGH or LOW before either rising or falling edge of the SCLK,
depending on SPI configuration. If both device is SPI hardware, then it
just matter to get configuration right and the hardware deal the rest
without worrying about the timing since they SPI standard.

Where the timing is important, is the speed to transfer data into
internal register and take it out quickly before collision occurs (via
flag which may block further SPI data...check datasheet). This is where
interrupts thread might be useful.

Good luck

Martin Riddle wrote:
> In-Line...
> "Sreeram S" <> wrote in message news:dj0ioc$gjk$...
> > Hello,
> >
> > I am trying to interface an MPC5554 procesor with 68HC908 processor
> > using SPI ( Serial Peripheral interface). MPC5554 is the Master CPU. I
> > have little experience in configuring the SPI in low level. I would like to
> > know the following.
> >
> > 1. What are the factors that I should consider while selecting the Clock
> > Polarity and Clock Phase? In my case both Master and Slave CPUs support
> > Clock Phase and Clock polarity of 0 and 1.
> >
> I see most devices clock data in on the falling edge, although some are on the rising edge.
>
> > 2. What are the factors that I should consider while deciding the delay
> > between the slave select signal and the first clock edge also the delay
> > between the last clock edge and the slave deselection?
> > i.e. The delay between Slave select going low and the first clock edge.
> >
> This is meerly a setup time for the internal gates, a safe bet is 1/2 clock cycle.
>
> > 3. What should be the optimum time difference between the transmition of two
> > message frames?
> >
> Not sure what you mean, the data rate is based on the clock, so skewing of clock and data makes no difference to the slave.
>
> > It will be very helpful if somebody can throw some light on this.
> >
> > Thanks and Regards,
> > Sreeram.
> >
> >

Who would write a SPI slave or master code without using interrupts?

"riscy" <> wrote in message news: oups.com...
> Try reading datasheet from Microchip, they cover SPI buses quite
> extensively with comprehesive diagram. The SPI bus serial data need to
> settle HIGH or LOW before either rising or falling edge of the SCLK,
> depending on SPI configuration. If both device is SPI hardware, then it
> just matter to get configuration right and the hardware deal the rest
> without worrying about the timing since they SPI standard.
>
> Where the timing is important, is the speed to transfer data into
> internal register and take it out quickly before collision occurs (via
> flag which may block further SPI data...check datasheet). This is where
> interrupts thread might be useful.
>
> Good luck
>
> Martin Riddle wrote:
> > In-Line...
> > "Sreeram S" <> wrote in message news:dj0ioc$gjk$...
> > > Hello,
> > >
> > > I am trying to interface an MPC5554 procesor with 68HC908 processor
> > > using SPI ( Serial Peripheral interface). MPC5554 is the Master CPU. I
> > > have little experience in configuring the SPI in low level. I would like to
> > > know the following.
> > >
> > > 1. What are the factors that I should consider while selecting the Clock
> > > Polarity and Clock Phase? In my case both Master and Slave CPUs support
> > > Clock Phase and Clock polarity of 0 and 1.
> > >
> > I see most devices clock data in on the falling edge, although some are on the rising edge.
> >
> > > 2. What are the factors that I should consider while deciding the delay
> > > between the slave select signal and the first clock edge also the delay
> > > between the last clock edge and the slave deselection?
> > > i.e. The delay between Slave select going low and the first clock edge.
> > >
> > This is meerly a setup time for the internal gates, a safe bet is 1/2 clock cycle.
> >
> > > 3. What should be the optimum time difference between the transmition of two
> > > message frames?
> > >
> > Not sure what you mean, the data rate is based on the clock, so skewing of clock and data makes no difference to the slave.
> >
> > > It will be very helpful if somebody can throw some light on this.
> > >
> > > Thanks and Regards,
> > > Sreeram.
> > >
> > >
>

"Martin Riddle" <> wrote in message
news:H2g5f.5981$hx.1782@trndny08...
> Who would write a SPI slave or master code without using interrupts?

Well, I for one. I just finished a design (hard- and software) where an AVR
controls two DDS's and two DACs. I used no SPI interrupts on the AVR side
simply because I didn't need to. (overkill)

Meindert

Meindert Sprang wrote:
> "Martin Riddle" <> wrote in message
> news:H2g5f.5981$hx.1782@trndny08...
>
>>Who would write a SPI slave or master code without using interrupts?
>
>
> Well, I for one. I just finished a design (hard- and software) where an AVR
> controls two DDS's and two DACs. I used no SPI interrupts on the AVR side
> simply because I didn't need to. (overkill)
>
> Meindert
>
>

I'd go along with that (at least for master code - I haven't implemented
an SPI slave). Frequently, the SPI bus runs so fast that it is far
easier just to wait for each byte transfer to complete rather than
implement interrupt systems. I've used micros where the interrupt
overhead is longer than the transfer time, so it is significantly faster
to use polling! Of course, this depends highly on the speed of the
processor - I'd hardly want an MPC5554 to wait around for an SPI
transfer (that's what its QSPI module is for), but it makes a lot of
sense on a 68HC908 chip (although you would want to interrupt on the
chip select).

I dont understand how the clock phase, polarity and delays between Slave
select and clock edges are related to using interrupts. In my case since
both master and slave are processors, all the parameters are configurable
and I wanted to know the factors that are considered while deciding these
values.
The tranmission and reception of one full message frame ( byte ) is handled
by hardware. Interrupts are only used for copying into tranmsit register and
copying from receive register. Polling does not suit my requirements since
both the processors are heavily loaded.
If the delay between slave select and first clock edge is meerly a set up
time for the gates, I feel one clock cycle of the slower device is a good
figure
Regarding the clock phase, both master and slave can latch data on both the
edges. so ideally speaking all the phase polarity combinations should work.


Regards
Sreeram.

"David Brown" <> wrote in message
news:4355f7bc$...
> Meindert Sprang wrote:
> > "Martin Riddle" <> wrote in message
> > news:H2g5f.5981$hx.1782@trndny08...
> >
> >>Who would write a SPI slave or master code without using interrupts?
> >
> >
> > Well, I for one. I just finished a design (hard- and software) where an
AVR
> > controls two DDS's and two DACs. I used no SPI interrupts on the AVR
side
> > simply because I didn't need to. (overkill)
> >
> > Meindert
> >
> >
>
> I'd go along with that (at least for master code - I haven't implemented
> an SPI slave). Frequently, the SPI bus runs so fast that it is far
> easier just to wait for each byte transfer to complete rather than
> implement interrupt systems. I've used micros where the interrupt
> overhead is longer than the transfer time, so it is significantly faster
> to use polling! Of course, this depends highly on the speed of the
> processor - I'd hardly want an MPC5554 to wait around for an SPI
> transfer (that's what its QSPI module is for), but it makes a lot of
> sense on a 68HC908 chip (although you would want to interrupt on the
> chip select).

Confusing top-posting fixed - see below.

Sreeram S wrote:

> "David Brown" <> wrote in message
> news:4355f7bc$...
>
>> Meindert Sprang wrote:
>>
>>> "Martin Riddle" <> wrote in message
>>> news:H2g5f.5981$hx.1782@trndny08...
>>>
>>>> Who would write a SPI slave or master code without using
>>>> interrupts?
>>> Well, I for one. I just finished a design (hard- and software)
>>> where an AVR controls two DDS's and two DACs. I used no SPI
>>> interrupts on the AVR side simply because I didn't need to.
>>> (overkill)
>>>
>>> Meindert
>>>
>>
>> I'd go along with that (at least for master code - I haven't
>> implemented an SPI slave). Frequently, the SPI bus runs so fast
>> that it is far easier just to wait for each byte transfer to
>> complete rather than implement interrupt systems. I've used micros
>> where the interrupt overhead is longer than the transfer time, so
>> it is significantly faster to use polling! Of course, this depends
>> highly on the speed of the processor - I'd hardly want an MPC5554
>> to wait around for an SPI transfer (that's what its QSPI module is
>> for), but it makes a lot of sense on a 68HC908 chip (although you
>> would want to interrupt on the chip select).
>
>
>

> I dont understand how the clock phase, polarity and delays between
> Slave select and clock edges are related to using interrupts. In my

They are not related - they are different (but relevant) issues.

> case since both master and slave are processors, all the parameters
> are configurable and I wanted to know the factors that are
> considered while deciding these values. The tranmission and reception
> of one full message frame ( byte ) is handled by hardware. Interrupts
> are only used for copying into tranmsit register and copying from
> receive register. Polling does not suit my requirements since both
> the processors are heavily loaded. If the delay between slave select

That's entirely up to you and your application requirements. Just make
sure the slave can respond to the interrupts fast enough - SPI
interfaces are generally not buffered in the way UART interfaces are.

> and first clock edge is meerly a set up time for the gates, I feel
> one clock cycle of the slower device is a good figure Regarding the
> clock phase, both master and slave can latch data on both the edges.
> so ideally speaking all the phase polarity combinations should work.
>

It should work fine with any settings as long as they are consistent.

> Regards Sreeram.
>

On Wed, 19 Oct 2005 11:15:05 +0200, Sreeram S wrote:

> I dont understand how the clock phase, polarity and delays between Slave
> select and clock edges are related to using interrupts. In my case since
> both master and slave are processors, all the parameters are configurable
> and I wanted to know the factors that are considered while deciding these
> values.
> The tranmission and reception of one full message frame ( byte ) is handled
> by hardware. Interrupts are only used for copying into tranmsit register and
> copying from receive register. Polling does not suit my requirements since
> both the processors are heavily loaded.
> If the delay between slave select and first clock edge is meerly a set up
> time for the gates, I feel one clock cycle of the slower device is a good
> figure
> Regarding the clock phase, both master and slave can latch data on both the
> edges. so ideally speaking all the phase polarity combinations should work.

As long as they're both the same, it should work regardless, yes.

And you shouldn't have to worry about that anyway, unless you're
bit-banging it at one end or the other - don't you just write a
byte to the SPI transmitter and it takes care of all the timing,
then when that byte shows up at the receiver, you get an interrupt,
right?

Thanks,
Rich