SPI slave select signals

Hi all,

In an SPI interface i have got 4 slaves and one master
What i wanted to know is wether the master can assert two slave
selects(SS_N) simultaneously OR is there a restriction that master can
assert only one slave select.

Does SPI standard dictate anything!!!

Any comments on this would be appreciated.

Regards,
Praveen

> In an SPI interface i have got 4 slaves and one master
> What i wanted to know is wether the master can assert two slave
> selects(SS_N) simultaneously OR is there a restriction that master can

The slave will drive its MISO pin while selected.

wrote:
> Hi all,
>
> In an SPI interface i have got 4 slaves and one master
> What i wanted to know is wether the master can assert two slave
> selects(SS_N) simultaneously OR is there a restriction that master can
> assert only one slave select.

Depends on the design of the master. The NIOS II used in the Altera
FPGA permits me to asers any number of the SPI select lines.

But also as has been pointed out if the slaves all try to respond with
data you've got problems on the SOMI singal line.

gm

wrote in news:1117455841.370215.303660
@f14g2000cwb.googlegroups.com:

> Hi all,
>
> In an SPI interface i have got 4 slaves and one master
> What i wanted to know is wether the master can assert two slave
> selects(SS_N) simultaneously OR is there a restriction that master can
> assert only one slave select.
>
> Does SPI standard dictate anything!!!
>
> Any comments on this would be appreciated.
>
> Regards,
> Praveen
>

The SPI can certainly assert multiple slave selects. The restriction is on
the slaves. No more than one slave can drive the MISO line at the same
time.

There are many SPI slave devices that are write only (No MISO connection).

Example:

1. Configuring multiple data converters with the same instructions. You
might reset the parts with the same instruction and address the parts
independently for gain settings.




--
Al Clark
Danville Signal Processing, Inc.
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