Re: Plea to SPARC laptop designers

>>>>> "Chris" == Chris Morgan <> writes:

Chris> Raymond Toy <> writes:
>> >>>>> "Mark" == Mark Gibson <> writes:
>>
Mark> SPARC architecture is flwawed in many ways, but it does run fast for
>>
>> Flawed in what ways?

Chris> still doesn't do out-of-order execution, still doesn't scale its
Chris> clockspeed as well as intel or amd chips, lower bandwidth interface to

These seem to be implementation issues, not architecture issues. And
the mythical sufficiently smart compiler would make out-of-order
execution not an issue.

But perhaps I'm confusing architecture with implementation.

Ray

Raymond Toy <> writes:

> >>>>> "Chris" == Chris Morgan <> writes:
>
> Chris> Raymond Toy <> writes:
> >> >>>>> "Mark" == Mark Gibson <> writes:
> >>
> Mark> SPARC architecture is flwawed in many ways, but it does run fast for
> >>
> >> Flawed in what ways?
>
> Chris> still doesn't do out-of-order execution, still doesn't scale its
> Chris> clockspeed as well as intel or amd chips, lower bandwidth interface to
>
> These seem to be implementation issues, not architecture issues. And
> the mythical sufficiently smart compiler would make out-of-order
> execution not an issue.
>
> But perhaps I'm confusing architecture with implementation.

Not that I know anything about it, but I compare Sparc to
all the other high-performance CPUs that TI fabs... oh, yeah...
TI _doesn't_ fab any other high-performance CPUs, do they?

Perhaps that's a clue.
-SEan

In article <>, Sean Burke wrote:
>
> Raymond Toy <> writes:
>
>> >>>>> "Chris" == Chris Morgan <> writes:
>>
>> Chris> Raymond Toy <> writes:
>> >> >>>>> "Mark" == Mark Gibson <> writes:
>> >>
>> Mark> SPARC architecture is flwawed in many ways, but it does run fast for
>> >>
>> >> Flawed in what ways?
>>
>> Chris> still doesn't do out-of-order execution, still doesn't scale its
>> Chris> clockspeed as well as intel or amd chips, lower bandwidth interface to
>>
>> These seem to be implementation issues, not architecture issues. And
>> the mythical sufficiently smart compiler would make out-of-order
>> execution not an issue.
>>
>> But perhaps I'm confusing architecture with implementation.
>
> Not that I know anything about it, but I compare Sparc to
> all the other high-performance CPUs that TI fabs... oh, yeah...
> TI _doesn't_ fab any other high-performance CPUs, do they?

No, just the majority of high-performance DSP (Digital Signal
Processing) chips. Similar speed & process requirements.

> Perhaps that's a clue.

Indeed.

Raymond Toy wrote:
>
> >>>>> "Chris" == Chris Morgan <> writes:
>
> Chris> still doesn't do out-of-order execution, still doesn't scale its
>
> These seem to be implementation issues, not architecture issues. And
> the mythical sufficiently smart compiler would make out-of-order
> execution not an issue.

Ah, out-of-order execution. I can just see it now - branch and
then test.

-am © 2003