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OV9653 image sensor interface problems

Discussion in 'Embedded' started by swami, Feb 11, 2008.

  1. swami

    swami Guest

    Hi,
    I am trying to capture the a single frame through omnivision 9653 an
    trying to write in sdram of ceva dsp processor.(i am new to this area)
    i followed the sccb protocol for communication(read/write) and the defaul
    values of the registers are read correctly.i can also be able to modify th
    ov9653 registers and the values are reflected back.so far ok

    for capturing the image (SXGA - 1280x1024 pixels)

    I found that HREF,HSTART,HSTOP,VSTART,VSTOP registers contain defaul
    values for SXGA format.

    Ex:
    HEND-HSTART = 1280 (reg.values by default)
    VEND-VSTART = 1024 (reg.values by default)

    Register CLKRC - pixel clk is half the inp.clk (inp.clk->25MHz)

    ceva fpga registers are programmed for image size,width,height
    and pointers to YCbCr.

    i am unable to get the data to memory.but End of Frame indication bit i
    set after the command to fetch data.but data is not available in memory.i
    there a problem in camera chip side or ceva dsp side.

    any help would be greatly appreciated.
     
    swami, Feb 11, 2008
    #1
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  2. On Monday, in article
    <>
    "swami" wrote:

    >Hi,
    >I am trying to capture the a single frame through omnivision 9653 and
    >trying to write in sdram of ceva dsp processor.(i am new to this area)
    >i followed the sccb protocol for communication(read/write) and the default
    >values of the registers are read correctly.i can also be able to modify the
    >ov9653 registers and the values are reflected back.so far ok
    >
    >for capturing the image (SXGA - 1280x1024 pixels)
    >
    >I found that HREF,HSTART,HSTOP,VSTART,VSTOP registers contain default
    >values for SXGA format.
    >
    >Ex:
    >HEND-HSTART = 1280 (reg.values by default)
    >VEND-VSTART = 1024 (reg.values by default)


    That assumes no blanking pixels and lines which one hopes is the case.
    >
    >Register CLKRC - pixel clk is half the inp.clk (inp.clk->25MHz)
    >
    >ceva fpga registers are programmed for image size,width,height
    >and pointers to YCbCr.


    Can the Ceva FPGA deal with Cb and Cr on different clock edges?
    That is the usual Omnivision trap that most people fall into.
    Check your data format and values.

    More importantly check what you connections are as to whether this
    is a demo board, a board you have made or someone has made for you.

    >i am unable to get the data to memory.but End of Frame indication bit is
    >set after the command to fetch data.but data is not available in memory.is
    >there a problem in camera chip side or ceva dsp side.
    >
    >any help would be greatly appreciated.
    >


    Without knowing more of the DSP and board in use it is difficult to help.


    --
    Paul Carpenter |
    <http://www.pcserviceselectronics.co.uk/> PC Services
    <http://www.gnuh8.org.uk/> GNU H8 & mailing list info
    <http://www.badweb.org.uk/> For those web sites you hate
     
    Paul Carpenter, Feb 11, 2008
    #2
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  3. swami

    swami Guest

    blanking period is there, i mentioned it incorrectly.

    For SXGA - 1280x1024 pixels:
    >>HEND-HSTART = 1280 -> active pixel time(reg.values by default)
    >>VEND-VSTART = 1024 -> active pixel time (reg.values by default)


    for VSYNC is 1050 (greater than 1024)including blanking time
    HSYNC is 1520(including blanking time) > 1280




    >On Monday, in article
    > <>
    > "swami" wrote:
    >
    >>Hi,
    >>I am trying to capture the a single frame through omnivision 9653 and
    >>trying to write in sdram of ceva dsp processor.(i am new to this area)
    >>i followed the sccb protocol for communication(read/write) and th

    default
    >>values of the registers are read correctly.i can also be able to modif

    the
    >>ov9653 registers and the values are reflected back.so far ok
    >>
    >>for capturing the image (SXGA - 1280x1024 pixels)
    >>
    >>I found that HREF,HSTART,HSTOP,VSTART,VSTOP registers contain default
    >>values for SXGA format.
    >>
    >>Ex:
    >>HEND-HSTART = 1280 (reg.values by default)
    >>VEND-VSTART = 1024 (reg.values by default)

    >
    >That assumes no blanking pixels and lines which one hopes is the case.
    >>
    >>Register CLKRC - pixel clk is half the inp.clk (inp.clk->25MHz)
    >>
    >>ceva fpga registers are programmed for image size,width,height
    >>and pointers to YCbCr.

    >
    >Can the Ceva FPGA deal with Cb and Cr on different clock edges?
    >That is the usual Omnivision trap that most people fall into.
    >Check your data format and values.
    >
    >More importantly check what you connections are as to whether this
    >is a demo board, a board you have made or someone has made for you.
    >
    >>i am unable to get the data to memory.but End of Frame indication bi

    is
    >>set after the command to fetch data.but data is not available i

    memory.is
    >>there a problem in camera chip side or ceva dsp side.
    >>
    >>any help would be greatly appreciated.
    >>

    >
    >Without knowing more of the DSP and board in use it is difficult t

    help.
    >
    >
    >--
    >Paul Carpenter |
    ><http://www.pcserviceselectronics.co.uk/> PC Services
    ><http://www.gnuh8.org.uk/> GNU H8 & mailing list info
    ><http://www.badweb.org.uk/> For those web sites you hate
    >
    >
     
    swami, Feb 12, 2008
    #3
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