If you mean you don't see the UxTXD register update in the SFR Watch Window,
there was a bug in that where some registers weren't being updated properly
(right value but showing in the wrong SFR). Zilog said it was fixed in 4.2.1,
but I have;t verified it myself.
As for the IRQ0 bit, are you trying to clear the bit before you take care of
the reason for the interrupt? It kind of sounds like that it what is happening.
The UART produces a continuous interrupt. If you don't take care of the reason,
the UART will reassert the IRQ0 flag about a cycle after you cleared it. This
is documented in the Interrupt Controller section of the eZ8 Product
Specification.
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