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80MHz clock, discrete logic

Discussion in 'Embedded' started by Steve at fivetrees, Feb 20, 2007.

  1. Hi folks,

    I have a fairly simple synchronous logic circuit, using a handful of
    flipflops and gates, which ordinarily I'd breadboard using HC TTL. However,
    it needs an 80MHz clock, which is too high for such families.

    I suspect I might need to look at FPGAs, CPLDs etc, but it's been a long
    time since I looked at these, and my timescales are short. Could anyone
    suggest either a family or technology with a short learning curve, adequate
    speed, and reasonable costs?

    TIA,

    Steve
    http://www.fivetrees.com
     
    Steve at fivetrees, Feb 20, 2007
    #1
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  2. Steve at fivetrees

    Stef Guest

    In comp.arch.embedded,
    The 74AHCT74 has a typical Fmax of 170MHz, 74F74 Fmax typ. 125MHz.
    Check the AHCT and F families, but there are also others. The logic section
    of the NXP website is a startingpoint.
     
    Stef, Feb 20, 2007
    #2
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  3. Steve at fivetrees

    Didi Guest

    ... Could anyone
    You will have little if any problems locating a family to do the job.
    Breadboarding at this speed is typically not practical, you are going
    to need power and ground planes.

    Dimiter
     
    Didi, Feb 20, 2007
    #3
  4. Steve at fivetrees

    linnix Guest

    You top posted and left out the important number: 80 MHz.
    More of a reason to use a single chip CPLD.
    Easy to find 200 to 300 MHz chips.
     
    linnix, Feb 20, 2007
    #4
  5. Thanks for the replies, chaps.

    Linnix: any particular CPLD family? I'm a CPLD virgin (although I have
    designed ASICs, about 20 years back...).

    Steve
    http://www.fivetrees.com
     
    Steve at fivetrees, Feb 20, 2007
    #5
  6. The original description of a "simple synchronous logic circuit, using
    a handful of flipflops and gates" does indeed suggest using a CPLD,
    but for the sake of completeness, it may be possible to simulate that
    logic in software. There are several small processors approaching or
    passing the 100 Mips mark.


    Roberto Waltman

    [ Please reply to the group,
    return address is invalid ]
     
    Roberto Waltman, Feb 20, 2007
    #6
  7. Steve at fivetrees

    linnix Guest

    Xilinx XC9536 should work.
     
    linnix, Feb 20, 2007
    #7
  8. What supply voltage(s) do you have ?

    Present fast/Low power CPLD Candiates are :

    Atmel ATF1502BE, in faster speed grade
    Tools: Suggest CUPL Boolean Design Entry, Similar to a C/ASM level of code.

    Lattice ispMach4000z family LC4032
    Tools: Suggest ABEL Boolean Design Entry, Similar to a C/ASM level of code.

    Xilinx CoolrunnerII XC2C32A -
    Tools: Suggest ABEL Boolean Design Entry, Similar to a C/ASM level of code.


    All tools are free, but Xilinx and Lattice have larger downloads than
    Atmel, because they do not bother to do a separate CPLD tool flow,
    so you get boatloads of FPGA support along for the ride.

    All the above are ISP via JTAG

    First two families have dual supplies, and very low power
    (some uA levels).
    Lattice have that, and also do a variant with an on-chip regulator
    that bumps Icc to a few mA, but they lack Hystersis option.

    -jg
     
    Jim Granville, Feb 20, 2007
    #8
  9. The circuit is for clock recovery of a 10MHz NRZ serial stream at TTL levels
    (i.e. 0-5V).
    <snip>

    Superb. And thanks to linnix too.

    /me goes off to do some reading

    Steve
    http://www.fivetrees.com
     
    Steve at fivetrees, Feb 20, 2007
    #9
  10. Steve at fivetrees

    Didi Guest

    You top posted and left out the important number: 80 MHz.

    I did not leave anything out.
    I just put it in the complete context I quoted
    at a place which apparently did not please you which is
    essentially your problem.

    I did post what I deemed relevant - the OP knew, as he had
    indicated, that CPLD was an obvious option. My suggestion
    may or may not have been obvious to him, it was informative
    in the context without restating what he obviously knew.

    But why bother about contents when we can concentrate
    on vital issues like top, bottom etc. posting religions.

    Dimiter
     
    Didi, Feb 20, 2007
    #10
  11. Steve at fivetrees

    linnix Guest

    I did not invent this format, just follow it.
    You knew, he knew and I knew, but hundreds of other readers might not
    know.
    It's public manners and simple considerations for other readers.
    I "top post" in emails, but "content post" in newsgroups.
     
    linnix, Feb 20, 2007
    #11
  12. if you need to power this from 5V, and accept 5V CMOS drive, that
    will move you back a generation - the ones I quoted are 1.8V cores
    3.3V IO, tho lattice MACH4000 claim 5V tolerance, provided it is not
    on too many pins...

    80Mhz is going to need some of the faster 5V parts.
    XC9536 in faster speed grades is one option.
    Expect around 60mA Icc

    Altera also have some older/higher power 5V CPLDs.

    -jg
     
    Jim Granville, Feb 20, 2007
    #12
  13. Steve at fivetrees

    Didi Guest

    You knew, he knew and I knew, but hundreds of other readers might not
    I agree with that, although he had mentioned it already in his
    first message.
    And I happen to think that combining the good parts of both
    top and bottom posting is the best practice nowadays.
    You objected to my omission of the "80 MHz" in my top-quoted
    part, perhaps you forgot to look at the subject line.

    Dimiter
     
    Didi, Feb 20, 2007
    #13
  14. Absolutely not. A 100Mips processor can only do one step in 10ns. That means
    that any output is at least 20ns lagging on an input. (read input, set
    output, two instructions). Compare that to the propagation delay of 125MHz
    logic, which is in the order of 4 ns.

    Meindert
     
    Meindert Sprang, Feb 20, 2007
    #14
  15. Steve at fivetrees

    linnix Guest

    That would cost at least 100 dollars, compared to a 2 dollars CPLD.
    Not too mention branchings as well.
     
    linnix, Feb 20, 2007
    #15
  16. Another thought - if this is simple, don't exclude the venerable 22V10,
    the lattice ispGAL22V10A series has the MHz, and 5V compliance
    with 3.3V Vcc.

    -jg
     
    Jim Granville, Feb 21, 2007
    #16
  17. Steve at fivetrees

    Tom Lucas Guest

    I was going to suggest the 22V10 as well but a quick google produced one
    that wasn't quick enough. Jim has found one though, so this could be a
    good route - I know of quite a few people who cut their teeth on the
    22V10 because it is nice a simple to work with.
     
    Tom Lucas, Feb 21, 2007
    #17
  18. There are more than I thought, with 5V Vcc : most 100+MHz, so not as
    quick as the lattice one, but still fine for 80MHz

    Atmel ATF22V10C - down to 5ns, 10ns and below look OK for 80MHz

    Atmel ATF750C - Two 22V10s in one package, 7ns variant, multiple clocks

    ICT/Anachip PEEL22CV10 - down to 7ns

    and ATF1502AS is a 5V part, that has a 10ns/7ns variants

    -jg
     
    Jim Granville, Feb 21, 2007
    #18
  19. Thanks, guys. I'm very grateful for the leg-up. I'll let you know how I get
    on.

    Steve
    http://www.fivetrees.com
     
    Steve at fivetrees, Feb 22, 2007
    #19
  20. Steve at fivetrees

    Dave Pollum Guest

    The Xilinx XC9500XL series CPLDs run on 3.3 volts and has 5 volt
    tolerant inputs.
    HTH
    -Dave Pollum
     
    Dave Pollum, Feb 23, 2007
    #20
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