A7n8x deluxe rev 2 and rev 1.04

Discussion in 'Asus' started by VP, Jun 17, 2004.

  1. VP

    VP Guest

    What is dif between Asus A7n8x deluxe rev 2 and rev 1.04 ?
    Both i can use Athlon XP 3200+ FSB 400 ?

    VP
     
    VP, Jun 17, 2004
    #1
    1. Advertisements

  2. VP

    Paul Mathews Guest

    I think you just need a bios flash to get 3200 running :)
     
    Paul Mathews, Jun 17, 2004
    #2
    1. Advertisements

  3. VP

    Paul Guest

    First of all, there are three boards in existence:

    A7N8X Deluxe Rev 1.04
    A7N8X Deluxe Rev 2.0
    A7N8X-E Deluxe Rev 1.01 <--- Latest board

    The Revision 1.04 board had some problems operating at FSB400/DDR400.
    Some people tried to fix this, by modifying a regulator on the
    motherboard, and claimed that increasing that voltage allowed the
    board to be run at a faster clock.

    The A7N8X Deluxe board had problems with the "BIOS Save Death" bug.
    As far as I know, this is fixed with the newer A7N8X-E Deluxe
    design. At least, I haven't seen any posts involving the A7N8X-E
    board and that problem.

    So, buy a A7N8X-E Deluxe Rev 1.01 and enjoy it. If you buy a
    A7N8X Deluxe (either 1.04 or 2.0), buy a BIOS Savior (ioss.com.tw)
    to go with it. The BIOS Savior will allow recovery from the BIOS
    Save bus.

    HTH,
    Paul
     
    Paul, Jun 17, 2004
    #3
  4. VP

    peter Guest

    I have never heard of the "BIOS save death" bug
    what is it??
    peter
     
    peter, Jun 18, 2004
    #4
  5. VP

    Paul Guest

    There are 75 hits here:
    http://groups.google.com/groups?q="bios+save+death"&ie=ISO-8859-1&hl=en

    Try the three terms BIOS save death and click "search for all terms".
    http://nforcershq.com/forum/search.php
    http://nforcershq.com/forum/viewtopic.php?t=37481&highlight=bios+save+death

    On most motherboards, CMOS settings are stored in a small RAM in the
    Southbridge. My personal theory, is the small RAM in the Nvidia
    Southbridge chip is non-functional, so the BIOS writers decided to
    store the CMOS settings inside the BIOS chip instead. A failure
    of an attempt to write to the BIOS chip (when you do Save and Exit),
    followed by the BIOS doing a hardware reset, results in a corrupted
    chunk of settings in the BIOS chip. Now, I have nothing to back
    this up, other than to say that it is highly unlikely that if
    the RAM in the Southbridge was working properly, there is no good
    reason for the BIOS chip itself to be corrupted, unless it is being
    used for a workaround as I outlined.

    HTH,
    Paul
     
    Paul, Jun 18, 2004
    #5
  6. VP

    Minotaur Guest

    Revision 1.XX boards are retarded from BIOS version 1003 onwards for
    200FSB compatibility. This can be proven in memory benchmarks and it is
    a good 10%+ slower than the revision 2.XX of the A7N8X motherboard when
    doing 197FSB+ (apx).

    For a good experiment if you have a Revision 1.XX board, try memory
    benchmarks from 196FSB to 200FSB. You shall find it retards the
    performance for 200FSB compatibility along the way. So in fact 197FSB
    could infact be faster than 200FSB on those boards because of that issue.

    Just something to remember that hasn't been reported a lot *8)

    Minotaur (8*
     
    Minotaur, Jun 18, 2004
    #6
  7. VP

    Doug Ramage Guest

    That's assuming you get a rev 1.xx board to do 197FSB. Mine is only stable
    below 184FSB (with any BIOS). :(
     
    Doug Ramage, Jun 18, 2004
    #7
  8. VP

    Kylesb Guest

    | In article <vJsAc.70$7d2.3@clgrps13>, "peter" <>
    wrote:
    |
    | > I have never heard of the "BIOS save death" bug
    | > what is it??
    | > peter
    |
    | There are 75 hits here:
    |
    http://groups.google.com/groups?q="bios+save+death"&ie=ISO-8859-1&hl=en
    |
    | Try the three terms BIOS save death and click "search for all
    terms".
    | http://nforcershq.com/forum/search.php
    |
    http://nforcershq.com/forum/viewtopic.php?t=37481&highlight=bios+save+death
    |
    | On most motherboards, CMOS settings are stored in a small RAM in the
    | Southbridge. My personal theory, is the small RAM in the Nvidia
    | Southbridge chip is non-functional, so the BIOS writers decided to
    | store the CMOS settings inside the BIOS chip instead. A failure
    | of an attempt to write to the BIOS chip (when you do Save and Exit),
    | followed by the BIOS doing a hardware reset, results in a corrupted
    | chunk of settings in the BIOS chip. Now, I have nothing to back
    | this up, other than to say that it is highly unlikely that if
    | the RAM in the Southbridge was working properly, there is no good
    | reason for the BIOS chip itself to be corrupted, unless it is being
    | used for a workaround as I outlined.
    |
    | HTH,
    | Paul
    |


    If this were true, then removing the battery (or jumpering the "clear
    CMOS" jumper) would not clear CMOS settings, keep in mind data written
    to the BIOS chip is permanent (until overwritten). I'm pretty certain
    the CMOS settings are stored in ram, maybe that ram is found in the
    Southbridge chip, I am not well versed on the NF2 chipset designs to
    be certain. I've read of the BIOS save death bug, I think it may be
    related to unstable BIOS settings or PS problems that create bad JUJU
    on the mobo during CMOS write operations, just my SWAG on the subject.
    The SIS735 chipset has a "lost CMOS" problem, which does not result in
    BIOS death, but rather, a resetting of the CMOS settings, and some
    have found the problem exists due to the temperature of the chipset at
    power on.
     
    Kylesb, Jun 18, 2004
    #8
  9. VP

    Paul Guest

    But the people affected by the bug, cannot recover by removing the
    battery or by following the "reset the CMOS" procedure. I can only
    conclude from this, that "Save and Exit" in the BIOS is doing
    something else. There is apparently an observable delay during
    this time, and it doesn't take time to write to the CMOS. Flashing
    a BIOS takes time, because writing an EEPROM has a fair delay per
    location, at least compared to the CMOS RAM in the Southbridge.

    I've never seen a credible explanation of the problem, so we're
    left to guess. Maybe someone who owns both an A7N8X Deluxe and
    an A7N8X-E Deluxe could comment on whether the delay after
    doing a "Save and Exit" is the same on both boards or not.

    Since every bit of info from Nvidia would be covered by an
    NDA, we're not likely to get an explanation or an admission
    of guilt.

    This article, as far as I'm aware, doesn't appear to be true.
    Setting the FSB to 100 via jumper, or a repaired BIOS from
    Nvidia didn't fix the problem either. And it is not strictly
    an overclocking issue either, as for some people it dies at
    stock settings. The "workarounds" trumpeted by some people, don't
    work for all, so product is still being RMAed to this day.

    http://www.theinquirer.net/?article=8250

    Paul
     
    Paul, Jun 18, 2004
    #9
  10. VP

    Kylesb Guest

    | In article <>, "Kylesb"
    |
    | > | > | In article <vJsAc.70$7d2.3@clgrps13>, "peter" <>
    | > wrote:
    | > |
    | > | > I have never heard of the "BIOS save death" bug
    | > | > what is it??
    | > | > peter
    | > |
    | > | There are 75 hits here:
    | > |
    | >
    http://groups.google.com/groups?q="bios+save+death"&ie=ISO-8859-1&hl=en
    | > |
    | > | Try the three terms BIOS save death and click "search for all
    | > terms".
    | > | http://nforcershq.com/forum/search.php
    | > |
    | >
    http://nforcershq.com/forum/viewtopic.php?t=37481&highlight=bios+save+death
    | > |
    | > | On most motherboards, CMOS settings are stored in a small RAM in
    the
    | > | Southbridge. My personal theory, is the small RAM in the Nvidia
    | > | Southbridge chip is non-functional, so the BIOS writers decided
    to
    | > | store the CMOS settings inside the BIOS chip instead. A failure
    | > | of an attempt to write to the BIOS chip (when you do Save and
    Exit),
    | > | followed by the BIOS doing a hardware reset, results in a
    corrupted
    | > | chunk of settings in the BIOS chip. Now, I have nothing to back
    | > | this up, other than to say that it is highly unlikely that if
    | > | the RAM in the Southbridge was working properly, there is no
    good
    | > | reason for the BIOS chip itself to be corrupted, unless it is
    being
    | > | used for a workaround as I outlined.
    | > |
    | > | HTH,
    | > | Paul
    | > |
    | >
    | >
    | > If this were true, then removing the battery (or jumpering the
    "clear
    | > CMOS" jumper) would not clear CMOS settings, keep in mind data
    written
    | > to the BIOS chip is permanent (until overwritten). I'm pretty
    certain
    | > the CMOS settings are stored in ram, maybe that ram is found in
    the
    | > Southbridge chip, I am not well versed on the NF2 chipset designs
    to
    | > be certain. I've read of the BIOS save death bug, I think it may
    be
    | > related to unstable BIOS settings or PS problems that create bad
    JUJU
    | > on the mobo during CMOS write operations, just my SWAG on the
    subject.
    | > The SIS735 chipset has a "lost CMOS" problem, which does not
    result in
    | > BIOS death, but rather, a resetting of the CMOS settings, and some
    | > have found the problem exists due to the temperature of the
    chipset at
    | > power on.
    |
    | But the people affected by the bug, cannot recover by removing the
    | battery or by following the "reset the CMOS" procedure. I can only
    | conclude from this, that "Save and Exit" in the BIOS is doing
    | something else. There is apparently an observable delay during
    | this time, and it doesn't take time to write to the CMOS. Flashing
    | a BIOS takes time, because writing an EEPROM has a fair delay per
    | location, at least compared to the CMOS RAM in the Southbridge.
    |
    | I've never seen a credible explanation of the problem, so we're
    | left to guess. Maybe someone who owns both an A7N8X Deluxe and
    | an A7N8X-E Deluxe could comment on whether the delay after
    | doing a "Save and Exit" is the same on both boards or not.
    |
    | Since every bit of info from Nvidia would be covered by an
    | NDA, we're not likely to get an explanation or an admission
    | of guilt.
    |
    | This article, as far as I'm aware, doesn't appear to be true.
    | Setting the FSB to 100 via jumper, or a repaired BIOS from
    | Nvidia didn't fix the problem either. And it is not strictly
    | an overclocking issue either, as for some people it dies at
    | stock settings. The "workarounds" trumpeted by some people, don't
    | work for all, so product is still being RMAed to this day.
    |
    | http://www.theinquirer.net/?article=8250
    |
    | Paul

    Yes, I too have noticed an extended delay during CMOS save operations
    at times, typically when changing ram timings and/or FSB settings,
    critical settings, as if some testing was underway. It would actually
    be fairly simple to test your theory, one would have to boot w/o any
    memory manager, use debug to read the entire BIOS into a file, reboot,
    make some CMOS changes, save the changes, then read the BIOS into
    another file and then do an FC on the files.
     
    Kylesb, Jun 18, 2004
    #10
  11. VP

    edde Guest

    My A7N8X Deluxe has had no problems running at 200mhz FSB ever since bios
    1004 and up. All default voltages too.
     
    edde, Jun 18, 2004
    #11
  12. VP

    Paul Guest

    Or you could use a flash utility and a DOS boot disk, and back up
    a copy of the BIOS with that. Then, make some changes, boot with
    the DOS disk again, and back up a second copy. (The disk may only be
    big enough to hold one image, so move the first file off, before
    the second boot.)

    I think CMOS is supposed to be on the order of 256 bytes, but
    depending on how the flash chip is arranged, a larger segment or
    page could be affected.

    This notion of storing things in the BIOS chip is not that
    strange. On the P2B, for example, microcode updates are cached
    as 2KB segments, in an area near the end of the flash chip.
    DMI and ESCD data is in there as well. That makes three areas
    in the BIOS chip that can be updated during POST. The BIOS
    contains flashing code, so the code necessary to add the ability
    to store 256 bytes of data would be trivial. The only question
    I've got, is how could they screw it up ?

    Paul
     
    Paul, Jun 19, 2004
    #12
    1. Advertisements

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.