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AT91: Correct way of using PDC & USART with interrupts? (newbie)

Discussion in 'Embedded' started by Mayank Kaushik, Jan 15, 2005.

  1. Hi,

    Im trying to use interrupts to send data out of the USART, employing
    the PDC. The chip im using is the AT91RM9200. I have configured the
    USART in loopback mode, sending and receiving data at the same USART.
    Ive configured the USART to interrupt whenever ENDRX is asserted.

    I have a doubt regarding the way the ENDTX interrupt is asserted.
    According to a timing diagram i got from the AT91CDROM related to the
    USART and PDC (AT91RM9200-BasicPDC) ,the ENDRX interrupt is asserted
    when the transmit counter reaches zero, and stays high till TNCR (next
    counter) is written (i do that in the interrupt handler).

    When the control enters the interrupt handler, interrupts will have
    been enabled, but ENDTX will still be high before a new value is
    written into TNCR..whats stopping more such interrupts from being
    asserted? is it the fact that the new interupt wil have the same
    priority as this one?

    Also, i had interrupts enabled for ENDRX assertion..but i was getting
    multiple interrupts, as soon as i switched on the device..the problem
    went away only when i followed the foll procedure for setting the usart
    and the PDC:

    first configure the USARt but dont enable RX\TX
    configure the PDC, load the transfer\receive buffer pointers n counts
    then enable RX and TX through the usart.
    only at the end enable interrupt for ENDRX on the USART

    but still, in the us_irq_handler if i do not disable ENDRX interrupts,
    im getting multiple interrupts. must i disable the interrupt? or will
    just putting in new values for the RX buffer in the PDC stop more

    thanx in anticipation
    Mayank Kaushik, Jan 15, 2005
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