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AT91RM9200 PLL Performance

Discussion in 'Embedded' started by raymund hofmann, Oct 7, 2003.

  1. Has anyone measured the performance of these PLL's concerning jitter / sidebands
    etc. ?

    I have my own board with the AT91RM9200 and checked the PLL's concerning jitter:

    With a Scope Jitter Analysis I get a interval error of about +-20nS over a time
    of 1ms for a output programmed to output PLLA (160MHz) divided by 8.

    PLLA register = 0x23af3f1d, Main Clock 4.9152Mhz (stable from a Crystal).

    I use the stanard loop filter as on the Demo Board.
    I also use seperate supply for the PLL's as proposed by Atmel.

    This jitter is very dependent on what the Processor is doing. If I stop it with
    the BDI2000, the PLL gets about 100 times "cleaner".

    When the software runs the frequency spectrum of the interval error (=pll vco
    input) seems to depend on some software loop frequency, which can be seen in the
    interval error plot.

    Also the cycle-cycle jitter is very high indicating crosstalk (inside
    AT91RM9200) way above the loop frequency (depending on loop filter) of the
    pll's, especially when the software runs.

    I tried Stabilizing all the supplies especially the PLL-supplies with nearly no
    effect. They are quite stable now, after i put a few big LOW-esr cap's on all
    supplies.
    The high frequency power stabilization should have been good already.

    I slowly get to the opinion it is not caused by my board, but only by the
    AT91RM9200.

    Or did I do something wrong ?

    The PLL's are very very bad compared to any PLL I know like:

    - ICS501
    - PLL's in Altera Cyclone
    - TLC2933

    Does anyone have a Board with the AT91RM9200 and check the PLL performance ?

    The very bad performance of the PLL's forbids their use for many external
    applications via the PCK's.

    I also fear that the bad performance should be accounted for by lowering the
    Maximum operating frequency of the ARM core about 10% from what the Datasheet
    says.

    Raymund Hofmann
     
    raymund hofmann, Oct 7, 2003
    #1
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  2. raymund hofmann

    Henry Guest

    Hi Raymund -

    Possible two things:
    1. big low-esr caps are not enough. Try out rf caps in the 1nF to 50nF range
    CLOSELY to the supply pins SEPARETING PLL and digital. AVX or Murata or
    American Tech Ceramics are good vendors thru GHz range. Feld-Wald-Wiesen
    types may have bad characteristics!
    2. Jitter is possible if the PLL have a post down-scaler. This is digital
    jitter you cannot avoid other than changing the PLL frequency dividing ratio
    to a better value. Try out...

    Surely Atmel decided to make the oscillator/PLL simplest in chip area.
    Running the cpu without activated PLL is maybe possible (I don't know
    details of datasheet).

    Regards -
    Henry

    raymund hofmann schrieb in Nachricht ...
     
    Henry, Oct 7, 2003
    #2
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  3. Obviously the RF produced in the target is somehow able to
    influence the PLL. You may have to separate the GND planes,
    and add filters to separate the supplies. A second voltage
    regulator is not sufficient. The jitter of a PLL is supposed
    to be somewhere in the ps range for the frequencies used.

    Rene
     
    Rene Tschaggelar, Oct 8, 2003
    #3
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