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ATA-1: PIO 0, 1, 2, 3 Timings versus CF I/O and Memory Space Timings

Discussion in 'Embedded' started by Tim Clacy, Oct 13, 2003.

  1. Tim Clacy

    Tim Clacy Guest

    A couple of CF+/ATA questions:

    1) PIO timings versus CF+ timings
    How do PIO cycle timings relate to CF+ address space timings? It seems the
    former is simply a cycle time, whereas the latter is device specific and has
    numerous components (address setup, command assertion, hold etc.). For
    instance, PIO 2 has a cycle time of 240ns, but the 1GB Microdrive has
    different address setup, command assertion wait and hold times for each of
    the three CF+ spaces (attribute, IO and memory).

    2) Using PIO in CF Common Memory Space
    Does I/O in CF common memory space use WAIT? In other words, is the PIO
    protocol always an asynchronous protocol regardless of the name of the space
    (attribute, IO, memory).

    In summary, I'm unclear about the relationship between the ATA PIO protocol
    timings and the Bus timings for the different CF address spaces.

    Many thanks in advance for any illumination an/or links to information.

    Tim Clacy, Oct 13, 2003
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