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C6x DMA: using dma_int0 to trigger a dma transaction on dma1

Discussion in 'Embedded' started by him, Aug 13, 2005.

  1. him

    him Guest

    TI C6x question here:

    the dma channels on the C6x can be setup such that they are
    synchronized to a number of events (32 total). I have experimenting
    with this such at

    ext_int7 triggers dma channel 0 to move data
    on completion dma0 generates dma_int0 (cpu int8)

    I would like to use dma_int0 to kick off another transaction but
    with dma channel 1. in short have dma channel 1 synchronized to
    the dma0's complete interrupt.

    the first part is functioning as expected, second part is where
    the problem lies. I know the dma0 complete interrupt is generated
    since I have a handler chained to it, but its not triggering a
    transaction on dma channel 1.

    Has anyone done something like this?
    Ill post code if anyone is interested.

    him, Aug 13, 2005
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  2. him

    him Guest

    Has anyone done something like this?

    int wdDmaCtrl0=0,wdDmaCtrl1;

    /*halt DMA0 and DMA1*/

    /*initialize DMA0 to transfer on int 7 and to reload
    using counterA and globalB*/

    DMA0_SRC_ADDR=(unsigned int)LCL_FIFO_IO;
    DMA0_DEST_ADDR=(unsigned int)LCL_INT_DATA_MEM;

    DMA_GADDR_B=(unsigned int)LCL_INT_DATA_MEM;

    /*initialize DMA1 to transfer on dmaint0 and to
    reload using counterB and globalC*/
    DMA1_SRC_ADDR=(unsigned int)LCL_INT_DATA_MEM;
    DMA1_DEST_ADDR=(unsigned int)LCL_FIFO_XX;

    DMA_GADDR_C=(unsigned int)LCL_INT_DATA_MEM;

    /*kick off the process*/





    dma0 operates as expected and theres a call to my dma0_int8
    (dma complete) isr. But dma1 isnt being triggered on dma0's
    completion as expected.

    data is read out of fifo_IO into idram (dma0)
    but not from idram into fifo_xx (dma1)

    Any ideas?
    him, Aug 14, 2005
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