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Can XP embedded re-enumerate the PCI bus when a system has booted?

Discussion in 'Embedded' started by Nial Stewart, Dec 8, 2009.

  1. Nial Stewart

    Nial Stewart Guest

    I'm about to design a PC104+ board for a client with a largish FPGA
    on it, this will be driven by an SBC running XP embedded.

    A couple of factors mean there could be a delay of ~1 second until the
    FPGA has fully configured and I'm worried the SBC could have enumerated
    the PCI bus before the FPGA is ready to respond.

    I know in Linux you can force the system to re-enumerate the bus fairly
    easily, can this be done in XP embedded too?

    Thanks for any pointers,

    Nial Stewart, Dec 8, 2009
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  2. Nial Stewart

    Jim Stewart Guest

    I've never seen it done.
    Jim Stewart, Dec 8, 2009
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  3. Nial Stewart

    D Yuniskis Guest

    I don't run XP <anything> so take this for what it's worth...

    In W2K, the *user* can force a SCSI bus to be re-enumerated
    under Device Manager (scan for hardare changes). Have you tried
    something like this?

    Can you also just have your BIOS pause for a second or two
    during the boot sequence? Or, other similar tricks to
    delay when the enumeration happens (is this process documented
    in detail anywhere that you could examine)?
    D Yuniskis, Dec 8, 2009
  4. Nial Stewart

    larwe Guest

    The simple way out of your predicament - which will not be broken by
    future OS updates or driver incompatibilities - is to have the FPGA
    hold the system in reset until it is ready for action.

    Having said that, yes, XPe *should* support doing this, but I do not
    know exactly how you would do it programmatically.
    larwe, Dec 8, 2009
  5. Nial Stewart

    linnix Guest

    The FPGA would not be able to hold the system in reset before it's
    loaded, without external hardware. It could be a simple capacitor,
    timer or micro. A micro can also handle the FPGA loading if necessary.
    linnix, Dec 8, 2009
  6. Nial Stewart

    larwe Guest

    The "external hardware" to which you refer could be as little as a
    resistor and a FET connected to a spare FPGA pin, to keep the system
    in reset until the FPGA's output goes from tristate to asserted.
    larwe, Dec 8, 2009
  7. Nial Stewart

    larwe Guest

    (BTW we can safely infer that there is hardware loading the FPGA- it's
    not being loaded from Windows - no way could Windows start and init
    the FPGA within 1 second!)
    larwe, Dec 8, 2009
  8. Nial Stewart

    linnix Guest

    But we don't know if the reset signal will also reset the FPGA. If
    depends on the design.
    linnix, Dec 8, 2009
  9. Nial Stewart

    Nial Stewart Guest

    Thanks for the feedback guys.

    Aye, I'm planning on Active Serial config for simplicity so the FPGA
    self loads from a serial flash device.

    Nial Stewart, Dec 9, 2009
  10. Nial Stewart

    Nial Stewart Guest

    In W2K, the *user* can force a SCSI bus to be re-enumerated
    This is early days of the project, I'm just thinking ahead.

    Is the SCSI bus not a special case to allow hot swapping of
    This might be an option if we did have a problem.

    Hopefully with a bit of forward planning we won't.

    Nial Stewart, Dec 9, 2009

  11. Some boards have a watchdog timer that could help(perhaps with a
    'latch-out' on the FPGA board to disallow a second reset?). Best
    approach is probably configure/customize the bios somehow.
    1 Lucky Texan, Dec 11, 2009
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