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Coolrunner 2 CPLD IO

Discussion in 'Embedded' started by Dave the Lurker, Feb 9, 2004.

  1. Hi,

    Taking advantage of a good exchange rate to the USA at present, I bought
    a coolrunner 2 CPLD evaluation kit from xilinx. I didn't check the IO
    standards of the supplied device though. I've now found it uses LVTTL
    amongst other things.

    The top end voltages of LVTTL is about mid range on standard bipolar TTL
    and in the linear area of CMOS. Does anyone have any experience of
    interfacing these three differing IO standards?

    I really want to interface to standard ROM / RAM, a z80 and RS232, is
    there a cheap easy fix for this ?

    Next time I read the datasheet!

    cheers,
    Dave
     
    Dave the Lurker, Feb 9, 2004
    #1
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  2. Dave the Lurker

    CBarn24050 Guest

    Hi, yes this lower voltage is a pain and is going to get worse.
     
    CBarn24050, Feb 9, 2004
    #2
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  3. Dave the Lurker

    Ville Voipio Guest

    Is there something wrong with 3.3 V CMOS? That should interface
    rather nicely to 5 V TTL. The problems start when you try to interface
    to 5 V CMOS, then the voltage is too low.

    - Ville
     
    Ville Voipio, Feb 9, 2004
    #3
  4. I agree this is fine for 3.3V CMOS, I want to interface to a mixture of
    standard CMOS and TTL though.

    Just wondering if the is a cheap and easy way to do this that will not
    fry the CPLD.

    The designs I have planned will probably never go above 4 MHz, so there
    is no problem if the quick fix craps out at speeds much greater than
    this.

    cheers,
    Dave
     
    Dave the Lurker, Feb 9, 2004
    #4
  5. It's not as bad as you might think.
    Newest lower voltage uC are offering 5V compatible IO, and the
    newest Lattice 4000 family, also have 5V compatible IO, as do
    the better LV logic families.

    Customers are demanding it, because besides legacy interfaces, some
    devices like PowerMOSFETS are not following the Vcc's down, so
    5V drive is important for them.
    CORE voltage will trend downwards, but it is only design laziness
    that also trends down the IO specs. It just takes more effort, and a
    tiny amount more silicon, to give 5V compatible IO.

    The 3.3V CR II will drive TTL which includes RAM.EPROM and RS232
    driver devices. You do need to watch HCMOS overdriving the CR
    inputs, and any 4000 series CMOS devices as loads.

    -jg
     
    Jim Granville, Feb 9, 2004
    #5
  6. Dave the Lurker

    Uwe Bonnes Guest

    : CBarn24050 wrote:

    : > Hi, yes this lower voltage is a pain and is going to get worse.

    : It's not as bad as you might think.
    : Newest lower voltage uC are offering 5V compatible IO, and the
    : newest Lattice 4000 family, also have 5V compatible IO, as do
    : the better LV logic families.

    : Customers are demanding it, because besides legacy interfaces, some
    : devices like PowerMOSFETS are not following the Vcc's down, so
    : 5V drive is important for them.
    : CORE voltage will trend downwards, but it is only design laziness
    : that also trends down the IO specs. It just takes more effort, and a
    : tiny amount more silicon, to give 5V compatible IO.

    : The 3.3V CR II will drive TTL which includes RAM.EPROM and RS232
    : driver devices. You do need to watch HCMOS overdriving the CR
    : inputs, and any 4000 series CMOS devices as loads.

    5 Volt static CMOS devices will nedd higher current standby current, as the
    input buffers will carry some currents, as both P and N transistor are
    partial switched on.
     
    Uwe Bonnes, Feb 9, 2004
    #6
  7. Thanks for all the comments, I think I have got it all going ok now.
    Nothing has let the magic smoke out yet anyway...

    cheers,
    Dave
     
    Dave the Lurker, Feb 15, 2004
    #7
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