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CPLD (CoolRunner failures)

Discussion in 'Embedded' started by Nigel, May 19, 2006.

  1. Nigel

    Nigel Guest

    has anyone experienced problems when operating Cool Runner (XPLA3)
    CPLDs near the capacity of their macrocells? specifically, i have two
    devices that have failed independently with hard short circuits to
    ground on the 3.3V power supplies. i have heard some anecdotal evidence
    that this can happen when too many of the macrocells are used. has
    anyone heard of this or seen it documented or reported elsewhere?
     
    Nigel, May 19, 2006
    #1
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  2. Sounds a strange idea - how does one macrocell, know that it's
    neighbours are used ?
    Check things like ESD ratings, and latchUp ratings.
    When did the failures occur ?

    -jg
     
    Jim Granville, May 19, 2006
    #2
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  3. Nigel

    Didi Guest

    Jim,
    strange things like that can indeed happen. On the oldest
    coolrunner, for which I have written my logic compiler, there
    was a possibility to use some more multiplexor paths than
    the manufacturers software was using (IIRC it was 40 vs. 36).
    I tried it only to discover that when it came to that, the
    chip was becoming unstable... so I lowered my limit as well.
    Perhaps it is about power distribution, who knows.

    Nigel,
    the fpga newsgroup should be better for this thread,
    Austin or Peter (both highly knowledgeable Xilinx employees)
    might be able to give some more info.

    Dimiter
     
    Didi, May 19, 2006
    #3
  4. Nigel

    Nigel Guest

    jg:
    thanks for your response. we have suspected ESD as a culprit. however,
    we have just recently performed an ESD survey of the vendor who has had
    these problems with the failed CPLDs, and they appear to be clean.
    Latch-up ratings are another matter - i'll look into this. thanks for
    the tip.
    N.
     
    Nigel, May 19, 2006
    #4
  5. Nigel

    Nigel Guest

    Dimiter:

    thanks for the info.

    the Vendor claims they have noticed unstable behavior when the CPLD
    gets filled up too. for one thing (and i'm not an expert in this area)
    timing seems to be more of an issue when the chip reaches capacity.
    more power is dissipated as the devicess reaches capacity too, which
    may be linked to the shorting problem.

    i'll try the FPGA news group as you suggested.

    N.
     
    Nigel, May 19, 2006
    #5
  6. That's rather a different case, even unique :)
    Coolrunners are low power devices - All I could think of was
    possibly longer programming times, for more device usage, but
    that is also a stretch...

    That's why the TIME-LINE of failures is important.

    Also, Vcc shorts do not sound like any device-mapping failures, but
    do sound like ESD/latchup ....

    -jg
     
    Jim Granville, May 19, 2006
    #6
  7. Don't rule out manufacturing problems, I remember a short on a CPLD
    (which just happened to be a Philips Coolrunner), but our clue was
    the short was not permanent. turned out to be a tiny ball of solder
    under a PLCC package, careful 'nudging' and heating a few pins in turn
    made it melt onto an existing pad only.

    Some conductive muck may have got on one batch of boards, that went to one
    site as well.
     
    Paul Carpenter, May 19, 2006
    #7
  8. Good point. Replacement=works, does not always mean the removed device
    is faulty, the OP should verify that failure on the removed devices.
    I was assuming his description was precise, but you could be right...

    -jg
     
    Jim Granville, May 20, 2006
    #8
  9. Nigel

    Nigel Guest

    the failure has manifested on the removed device. we have delidded the
    device and verified the short on the die. however, we have not ruled
    out that contamination external to the package may have caused the
    failure in the first place.

    the vendor claims shorting can happen in devices near capacity. i have
    heard of no other examples of this. other modules that have the same
    CPLD with the same program have not failed.

    bottom line: we suspect ESD damage due to mishandling.

    thanks for the responses.
    N.
     
    Nigel, May 21, 2006
    #9
  10. Nigel

    Peter Alfke Guest

    "Vendor" would have to be Xilinx, but I cannot believe that statement.
    Filling a low-power CPLD to capacity does not create a Vcc-to-GND short
    circuit.
    That is not even an urban legend, it's just silly.
    Peter Alfke, Xilinx Applications
     
    Peter Alfke, May 21, 2006
    #10
  11. Who is the 'vendor' you refer to ?
    -jg
     
    Jim Granville, May 21, 2006
    #11
  12. the vendor claims shorting can happen in devices near capacity.
    So, all your users buy from you directly?
     
    MikeShepherd564, May 21, 2006
    #12
  13. It could conceivably cause some kind of ground bounce leading to
    latchup of the parasitic SCR and thence to death by overheating of the
    die if the supply is capable of delivering the amps.

    Is the ground and bypass situation on the chip close to ideal? (at
    least 4-layer board with gnd and Vdd planes and lots of bypass
    capacitance)?

    I have a different kind of part (micro) from a different vendor that
    manages to tell the difference between what should be a simple CMOS
    input (no pullups or anything like that) grounded and the same input
    grounded through a 1.2K resistor.


    Best regards,
    Spehro Pefhany
     
    Spehro Pefhany, May 21, 2006
    #13
  14. Latch-up is mainly a current injection effect, and can be reduced if
    the lead-connections to the outside world have series impedance, or
    series impedance + external clamps, in severe cases.
    In devices with internal Vcc-IO clamp diodes, you do need to watch
    lifting Vcc effects, from long duration/significant values clamp
    currents, and power supplies that do not sink (most do not).
    Low power CPLDs need attention in this, because their own load
    currents are very low.

    On the PLDs we've tried to create LatchUp on, -ve pulse latchup was
    easier than +ve ( but still >> 100mA) and +ve latchup needed quite
    massive over-voltages to get enough current (higher clamp impedences)
    - so in that direction, pin failures are likely to happen at the same
    time, or first.

    -jg
     
    Jim Granville, May 21, 2006
    #14
  15. Nigel

    Falk Brunner Guest

    Could also be a power-up sequence issue. When different voltages are
    onboard and another IC connected to the CPLD is power up much ealier and
    drives the (still unpowered) IOs of the CPLD, latchup can happen too.
    Naaaaa, I wouldnt like to develop paranoia on this. I think a double
    layer for this CPLD is just fine, with some 100nF placed close to the CPLD.

    Regards
    Falk
     
    Falk Brunner, May 21, 2006
    #15
  16. The reasoning here is that a more fully utilized CPLD has more nodes
    switching very quickly and virtually the same instant, which in turn
    means more volts across fixed stray layout, package and die
    inductance.
    Sure, however I fail to see how power sequencing issues would lead to
    different results depending on the percentage of the CPLD which is
    used.
    Maybe, but it's hard to make a marginal layout when full power planes
    are employed, even with an dumb-as-a-post autorouter. Single and
    double-sided boards offer far richer opportunities in this department.


    Best regards,
    Spehro Pefhany
     
    Spehro Pefhany, May 21, 2006
    #16
  17. Nigel

    Falk Brunner Guest

    Right, but this is only a qualitative statement. What matters is
    quantity. So how big is the overall inductance? How much does voltage
    drop increase between a almost empty and a almost full device?
    Answering these question (which is not so easy) may yield the answer,
    that there is plenty of margin left. Ind I guess Xilinx did quite alot
    of testing with fully utilized devices.
    Ask Mr. Murphy ;-) Maybe its just one critical IO that is used or not.

    Regrds
    Falk
     
    Falk Brunner, May 21, 2006
    #17
  18. Ask Mr. Murphy ;-) Maybe its just one critical IO that is used or not.[/QUOTE]

    If it is true that only boards to one site with same program as other boards
    fails, my money is on environmental or manufacturing.


    I.E. something on the site is different to screw things up - ESD, other
    damage to boards, miswiring, latchup or other screw ups because
    of sequencing of external events.

    Manufacturing caused those boards to have something wrong with that
    batch.

    All of which could still be a marginal issue in the design, that site
    ensures happens.
     
    Paul Carpenter, May 21, 2006
    #18
  19. Nigel

    Nigel Guest

    the vendor (i cant reveal who that is) is using the CoolRunner in a
    design.
    it is not Xilinx.
    N.
     
    Nigel, May 22, 2006
    #19
  20. Nigel

    Nigel Guest

    cannot say.
    vendor is not Xilinx.
     
    Nigel, May 22, 2006
    #20
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