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CPU Interface setting on NF2 mobos (Dfi NF2 Ultra series esp)

Discussion in 'Overclocking' started by Nil Einne, Jan 13, 2004.

  1. Nil Einne

    Nil Einne Guest

    Hey all,

    Could someone explain what CPU interface does? I haven't managed to
    find any explanation other then it might improve overclockability. One
    site suggested it had something to do with fast decode but since it
    was only in this site and only in one review, I'm not really that
    sure. In any case, I don't know what fast decode is. I gather that
    some bioses have it as aggresive and optimal and some have it as
    enabled and disabled but all seem to claim it improves
    overclockability but may reduce stability.

    I have come across one site claiming it increases overclockability but
    reduced performance although how wasn't explained. Also, the Dfi beta
    bios information appears to suggest that aggressive is good for
    overclocking but below 10x multiplier there's lost memory bandwidth
    (or perhaps there always is, it just wasn't properly reported?).

    I'm really confused and would really like some clarification. Thanks
    for all help.
     
    Nil Einne, Jan 13, 2004
    #1
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  2. Hi,
    if you can get it enabled, use it. It gives me higher memory bandwidth, but
    I have problems having it enabled above 200MHz-FSB
    --
    Wayne ][

    Barton (AQXEA) XP2500+ @ 2.2GHz (10x220) - 1.75vCore
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    Wayne Youngman, Jan 13, 2004
    #2
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  3. Nil Einne

    Top-poster Guest

    It sets the latency twixt CPU and chipset.


     
    Top-poster, Jan 13, 2004
    #3
  4. Nil Einne

    Ben Pope Guest


    That would be my guess... since enabling it or setting it to aggressive
    raises memory bandwidth (which is usually measured across the FSB as the
    limiting factor). Since the frequency of the FSB is fixed, to improve
    performance you need to reduce latency.

    Ben
     
    Ben Pope, Jan 13, 2004
    #4
  5. Nil Einne

    Top-poster Guest

    Then, good guess.


     
    Top-poster, Jan 13, 2004
    #5
  6. Nil Einne

    Cheah TE Guest

    | Since the frequency of the FSB is fixed, to improve
    | performance you need to reduce latency.

    What if bios is already set to follow dimms' spd i.e. eeprom ?
     
    Cheah TE, Jan 14, 2004
    #6
  7. Nil Einne

    Ben Pope Guest


    What about it?

    We're discussing the timings of the FSB, not the memory bus.

    Ben
     
    Ben Pope, Jan 15, 2004
    #7
  8. Nil Einne

    Top-poster Guest


    This is a known issue - set manually, not with SPD.
     
    Top-poster, Jan 15, 2004
    #8
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