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E3500 questions

Discussion in 'Sun Hardware' started by Andrew Tyson, Jun 26, 2003.

  1. Andrew Tyson

    Andrew Tyson Guest

    Hi,

    I have a few questions relating to the E3500 and CPU/memory boards;

    1. Does each CPU/memory board require SIMMs (i.e. is it possible to install
    a CPU memory board with CPUs, but no memory into a E3500 that already has
    one or more CPU/memory boards with memory)? My guess is that all boards
    require memory modules.

    2. Do the CPUs on a given CPU/memory board only access the physical memory
    on the board that they are installed? If so I presume that it is advisable
    to have memory evenly dispersed amongst the CPU/memory boards.

    3. Is it possible/advisable to have a heterogeneous mix of CPUs on different
    boards in the E3500 (e.g. one board with 400Mhz (8MB cache) CPUs and another
    board with 400MHz (4MB cache) CPUs )?

    Thanks and regards,
    Andrew
     
    Andrew Tyson, Jun 26, 2003
    #1
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  2. Andrew Tyson

    Mike Jones Guest

    Boards do not require memory. So if, for instance, you have a machine
    with 2 CPUs and 2GB of memory on one CPU board, you can add a second CPU
    board with 2 CPUs and no memory. No problem.
    CPUs can access all memory in the system. It's an SMP machine. All
    memory is equally accessible to all processors. There is sometimes an
    advantage of spreading memory evenly across boards in that you get
    better memory interleave, but that's a pretty small effect in most
    cases.
    Possible but not advisable. If you mix CPU speeds, all the CPUs will run
    at the speed of the slowest CPU in the system.
     
    Mike Jones, Jun 26, 2003
    #2
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  3. No. You only need, at a minimum, one bank of SIMMs. This can be
    shared by all the CPUs on each CPU/Memory board.
    They can access all the memory on all the CPU/Memory boards.
    However, there is a small issue of latency when accessing memory
    not on the local board. So it would be better to have SIMMs
    spread out if you have enough. For example, if you have 2
    CPU/Memory boards and two banks of SIMMs, put one bank on
    each board.
    The CPU speed and bus/clock speed are related. If you mix different
    speed CPUs the bus will drop down to the match the lower speed ones.
    For the same speed but different cache sizes, its not an issue. The
    bus will run at the correct speed. Having different cache sizes will
    affect performance, however. In particular, with databases doing SMP.
    For mixed applications, its not really an issue but pinning processes
    to CPUs would be advisable.

    -am © 2003
     
    Anthony Mandic, Jun 26, 2003
    #3
  4. Andrew Tyson

    Scott Howard Guest

    Technically they are DIMMs, not SIMMs (Dual as opposed to Single)
    All Ultra-SPARC II machines have fixed CPU<->Memory latency, regardless of
    which board the CPU and memory are on. ie, the time to access memory on
    another board is the same as the time taken to access memory on the same
    board as the CPU.

    This changes with some of the US-III machines (3800-6800 to some extent,
    and SF12/15K to a larger extent), which is why Solaris now has a feature
    called MPO (Memory Placement Optimisation) which allows for "smarter"
    layout of memory (basically keeping a processes CPU and memory as "close"
    as possible to each other).
    This is a good idea, but for redundancy, not performance. If you evenly
    share the memory across multiple boards and one system board fails, you
    will only loose some of your memory, not all of it.
    Mixed speed CPUs are NOT supported on US-II machines. From memory on
    everything but an E10k attempting to do so will result in half of the CPUs
    being failed by POST (on an E10K it's actually possible to "underclock" a
    CPU, so say have a 400Mhz CPU running at 333Mhz)

    From memory the official line with mixed speed E-cache is that they are
    supported between boards, but not supported on the same board. Unofficially
    you can mix them on the same board, but I think it drops both CPUs down
    to the lower Ecache size (Make sure you're running the latest firmware
    though, there was a bug a few versions back where mixed cache sizes on
    the same board broke things)

    US-III is a completely different matter. You can't mix E-cache sizes (simply
    'cos CPUs only come in one Ecache size :), but you can mix CPU speeds (with
    a few exceptions).

    Scott.
     
    Scott Howard, Jun 27, 2003
    #4
  5. No, this is simply mnot true. All CPU:s will run at the lowest freq.
    Mixing cache sizes should work aswell.
    I've personally run 250 CPUs with 1 and 4 MB cache simultainiously.
    I've seen systems where 400/8 modules were underclocked to 250MHz.

    /wfr
    Fredrik
     
    Fredrik Lundholm, Jun 27, 2003
    #5
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