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Fibre Optic Cable Linking

Discussion in 'Embedded' started by Michael Karas, Jul 24, 2010.

  1. I am looking for reference materials and design ideas for implementing a
    customized high speed synchronous serial communications solution over a
    fiber optic cable pair (one for Rx and the other for Tx). This link
    would be between two system boxes and would require a net data rate
    throughput of 100 megabits per second. I would anticipate that the link
    logic would be implemented in FPGA technology on each end. The primary
    function would be to deliver about 100 bits of internal FPGA state on
    each end to the links to the other end in frames that would occur once
    per 1 millisecond. One end would act as a master framer while the other
    end would be a target responder to accept the master 100 bits/frame and
    respond back with a return frames of 100 bits. The design will need to
    be of a continuous flow nature such that to the master end of the link
    the would literally comprehend the target end as a remote extension end
    of itself. State control logic in the master end would simply be
    reflected to the target end with 1 msec latency and the status of the
    target end would appear back at the master end with an additional 1 msec
    latency.

    What would be the best recommended modulation technology for the FPGA to
    generate the frames going out onto the fiber optic cable? The protocol
    used would need to be one such that the receiving end can recover
    clocking from the data stream. Is good old Manchester encoding the best
    for this or is it better to use one of the bit stuffing protocols?

    Any discussion on the topic welcome.
     
    Michael Karas, Jul 24, 2010
    #1
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  2. If you want to save yourself the FPGA development effort, Cypress do the
    CY7C9689 Taxi Communications chip which will implement a point to point at
    up to 200Mbps. It is a proprietary protocol but for a point to point link it
    should suit.

    --
    ********************************************************************
    Paul E. Bennett...............<email://>
    Forth based HIDECS Consultancy
    Mob: +44 (0)7811-639972
    Tel: +44 (0)1235-510979
    Going Forth Safely ..... EBA. www.electric-boat-association.org.uk..
    ********************************************************************
     
    Paul E. Bennett, Jul 25, 2010
    #2
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  3. The Cypress device you suggested is a clever looking part. It would
    still require some FPGA interface work as the data coming and going must
    be packetized from the internal FPGA 100-bit wide mode into the
    necessary 8-bit or 10-bit widths to feed into or out of the CY7C9689A.
    One concern is the device cost.

    At Mouser:
    CY7C9689A-AXC (com) @1-$69.23 @50-$66.08
    CY7C9689A-AXI (ind) @1-$104.02 @50-$86.68

    At Digikey:
    CY7C9689A-AXC (com) @1-$78.61 @100-$66.69
    CY7C9689A-AXI (ind) @1-$99.07 @100-$83.59

    At these prices it is likely to be a non starter if the FPGA cost to
    implement similar transport logic costs less.
     
    Michael Karas, Jul 25, 2010
    #3
  4. I'll study these solutions and see if they are at all suitable. A quick
    look at some TI devices reveal that they interface via SPI and that is
    not very useful in the case I have in mind.
     
    Michael Karas, Jul 26, 2010
    #4
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