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Flash mcu with SPI slave capable of 16MHz operation?

Discussion in 'Embedded' started by Antti, May 7, 2007.

  1. Antti

    Antti Guest

    I guess none available :(

    all seem limit to clock/4 or something

    but maybe I have missed some good part?

    Antti, May 7, 2007
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  2. Antti

    Maki Guest

    Take look at Philips LPC213x. SPI1 port frequency is calculated as
    follows: PCLK / (CPSDVSR * [SCR+1]).
    PCLK=60MHz, CPSDVSRmin =2 and SCR =0. Wich gives 30MHz!

    Maki, May 7, 2007
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  3. Antti

    Antti Guest


    you mean SSP ?
    SPI on LPC213x ia 1/8 of clock

    and for the SSP, gosh I think I need to go to elementary school or
    the document called "datasheet" includes virtually info about the SSP
    hope I find the correct datasheet also somewhere.
    if it really can handle 16mhz spi slave would be real nice

    thanks for the hint
    Antti, May 7, 2007
  4. Antti

    Dominic Guest

    Hello Antti,

    you have to look for the User's manual to find some meaningful documentation
    on the LPC2000 chips.

    The LPC213x UM says that when the SSP is used in slave mode, CPSDVSRmin is
    12 instead of 2, leading to a much lower frequency.


    Dominic, May 7, 2007
  5. Antti

    Maki Guest

    Thank You Dominic for a correction. I was supeficial.

    Best regards,
    Maki, May 7, 2007
  6. Antti

    Antti Guest

    Thanks Dominic!

    well this clears it for LPCxxxx :(
    and the user manual, I LOOKED FOR it at NXP website, its not there !
    (or hidden...)
    but google finds from mct.net :)

    thanks again
    and I keep looking for alternatives

    Antti, May 7, 2007
  7. Hi Antti,
    No, I think you are pretty much right.
    There are ones that will run typically /2 on master mode,
    but to operate in slave, takes more clocks (/4 or more), and some are
    many more(/10).

    So, generaly you'd need to target the fastest clock speeds, to
    get 16MHz, > 64MHz, or 128MHz is suggested.

    The AT32UC3A0512 looks fast in master, but I did not
    see a fMAX in slave mode.
    AT91SAM9260 info suggests ~32ns in slave, but lacks any
    CLK ratio specs, and there must be some.

    AT91SAM9XE512 is the upcomming flash ARM9, which is likely
    to have a high CPU Clk, so give better peripheral speeds.

    The C8051F41x slave is /10 full duplex, and /4 half duplex, makes
    5Mhz and 12.5Mhz slave speeds.

    AT89LPxx spec /4 in fastest SPI mode.

    LPC24xx specs CLK/8 as fmax.

    I think they all sample the SPI pins, as being simplest.
    Easiest to design and test.
    In theory, I guess one could dual port a SPI, and have a genuine
    high slave speed, but that's not an area the designers have targeted.

    You could always use a CPLD, if it must run in slave mode ?

    Jim Granville, May 7, 2007
  8. Antti

    Antti Guest

    Hi Jim,

    you made summary of what I was afraid the situation is.
    BOM cost needs to be around 3USD and it must be available now.

    I possible have to go CPLD+MCU (BOM 2.8USD) or even FPGA+MCU (BOM
    there is also PCB space constraints so only can use microBGA or small
    if I can fit the needed stuff into XC9572XL then I may use that
    the function needed is rather simple, so I was hoping to reduce the
    count to flash mcu only. optionally could use 1 FPGA but that would
    kill BOM limits.

    the gadget is special serial memory emulator,
    that need to handle certain protocol at 16mhz.
    it doesnt directly map to any available spi flash memories, so need
    kind of serial protocol converter.

    Antti, May 7, 2007
  9. How much code Size / CPU muscle appx do you need ?

    Jim Granville, May 7, 2007
  10. Subject: Flash mcu with SPI slave capable of 16MHz operation?

    Why need a flash MCU? Protection?
    An AT91SAM9261 has 160 kB of internal SRAM which
    can be used for code & data.
    It can load the SRAM from a cheap 1 Mbit serial flash.

    Running the bus at 96 MHz you have 96/16 = 6 times
    overclocking which should be good enough!

    Your CPU will run at 200 MIPS+ as well from the TCM.
    Ulf Samuelsson, May 7, 2007
  11. Hi Ulf,
    Antti since came back with another detail - a $3US budget ;)
    - but while you are here, what is the MAX Slave clock
    speed for the AT32UC3A0512 ?

    I did find the infineon XC2200 specs this

    [SSC/SPI/QSPI (synchronous serial channel with or without data buffer)
    – maximum baud rate in slave mode: fSYS
    – maximum baud rate in master mode: fSYS / 2
    – number of data bits programmable from 1 to 63, more with explicit stop
    – MSB or LSB first
    – optional control of slave select signals]

    Not sure if that is a typo, as they claim faster Slave than Master ?,
    - out of step with everyone else.

    Nice part/peripheral, but the XC2200 family are starting at the top,
    and releasing downwards (as is the AT32UC3A0512 ), so neither
    are going to hit $3 until smaller ones come along...

    Jim Granville, May 7, 2007

  12. My firends at Atmel Nantes says that the SPI slave will work up to
    CPUCLK/2, so 32 MHz should be possible with the AT32UC3A0512.
    While this wont meet the $3, the AT32UC3B family should maybe be
    in the right price range, probably not in single qty though.
    Ulf Samuelsson, May 9, 2007
  13. Thanks Ulf. Is this true of all Atmel 32 bit SPI peripherals ?
    (SAM7 and SAM9 ? ).
    Where I have seen a 2x ceiling before, it
    is sometimes qualified with Tsu,Th,Jitter, and duty cycle margins,
    to be appx 2.5x as a 'practical ceiling'. It may be that some of
    the 4x SPI specs are just rounding that again.

    Any schedule for the AT32UC3B family yet ?

    I'd imagine Antti's BOM target is not single Qty, as worrying about that
    detail of price only matters for > 10K levels.

    Jim Granville, May 9, 2007
  14. Antti

    Antti Guest

    your guess is very correct.
    BOM cost difference of 0.80 USD matter at qty >10K

    who also looks forward to see more AVR32 flash chips
    Antti, May 10, 2007
  15. The AVR32 SPI implementation does not synchronize the
    input clock with the internal clock.
    Instead the input clock will clock the flip flops
    in the SPI shift register and synchronization is
    done when the complete byte is read/written to holding register.
    Looking at the AT91 SPI block diagram shows that this is the same.
    No synchronization of the SPI clock in slave mode.

    I guess that any SAM7S should do as well then.
    Many are!!!
    Ulf Samuelsson, May 11, 2007
  16. So, then where-from the SYSCLK/2 limit ?.
    What you describe should be able to clock faster on the slave ?

    Jim Granville, May 11, 2007
  17. I do not know how the synchronization for the holding register works...
    Ulf Samuelsson, May 11, 2007
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