help about OV7620 i want to interface it with spartan 3

Discussion in 'Technical Support' started by hackdz, Jun 1, 2012.

  1. hackdz


    Apr 15, 2012
    Likes Received:
    good morning all
    i am a student in master degree and i am doing a project about a design and implementation an ov7620 interface on FPGA my board test is a spartan3a kit starter.
    my question is about interfacing digital camera ov7620 with fpga spartan 3a to show the streaming to VGA monitor, but i am a beginner in VHDL, but after some knowledge in this field i understand some basic and know i am trying to write a VHDL block for this interface and testing this directly here is my begin program but i don t know how to continue and for this reason i need assistance .

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    library UNISIM;
    use UNISIM.VComponents.all;

    entity cam_interface is
    port (
    clk_i : in std_logic;
    rst_i : in std_logic;

    -- camera side

    Y_i : in std_logic_vector(7 downto 0);
    UV_i : in std_logic_vector(7 downto 0);
    PCLK_i : in std_logic;
    HREF_i : in std_logic;
    VSYNC_i : in std_logic;

    -- FPGA side
    R_o : out std_logic_vector(7 downto 0);
    G_o : out std_logic_vector(7 downto 0);
    B_o : out std_logic_vector(7 downto 0);

    -- this signal indicate a new line on falling edge and rising edge
    new_pix_o : out std_logic;
    new_line_o : out std_logic;
    new_frame_o : out std_logic;
    rst_camera_o : out std_logic
    end cam_interface;

    till here i don t know how to continue than hope that i will get some help from the members
    i want to get the output 16/8 bit Raw RGB
    i know for this i must write some register with I2C interface

    thankssssssss in advance
    hackdz, Jun 1, 2012
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