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Help on Looser-Take-All / Winner-Take-All circuit

Discussion in 'Embedded' started by Etantonio, Mar 15, 2005.

  1. Etantonio

    Etantonio Guest

    Good morning,
    a friend of mine have inserted this post on a Forum I created on my site
    www.etantonio.it/en , this is the question :

    "Someone knows something about LTA/WTA circuits?
    I mean the best approach to the problem,
    the best topology and all that can be usefull
    to design an accurate and high-speed LTA?"

    I don't know the answer, if you know it please post it just following this link:

    http://www.etantonio.it/Forum/topic.asp?TOPIC_ID=15

    Many Thanks,

    Eng. Antonio D'Ottavio

    www.etantonio.it/en/
     
    Etantonio, Mar 15, 2005
    #1
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  2. Etantonio

    CBFalconer Guest

    No way I am going to bother with various private forums. Usenet is
    quite satisfactory, thank you. Ask here, read here.

    It sounds vaguely like a voting circuit, which is a key factor in
    high reliability systems built around redundant modules. The truth
    table for a three input component might be:

    input output failed node id
    000 0 0 = 00 (binary)
    001 0 1 = 01
    010 0 2 = 10
    011 1 3 = 11
    100 0 3 = 11
    101 1 2 = 10
    110 1 1 = 01
    111 1 0 = 00

    and all inputs other than 000 and 111 indicate a failure
    somewhere. You can build this out of three 2 input nands, and one
    3 input nand. Analog methods can cut the component count.
    Implementing a failed node id may be useful in servicing.

    Of course, quis custodes custodiet applies.
     
    CBFalconer, Mar 15, 2005
    #2
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  3. Etantonio

    Etantonio Guest

    Many thanks for your answer,
    I'll forward it to my friend,
    Bye ...

    Antonio
     
    Etantonio, Mar 16, 2005
    #3
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