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how can a newer processor have worse L1 cache?

Discussion in 'Intel' started by Anne Onime, Apr 6, 2011.

  1. Anne Onime

    Anne Onime Guest

    I have seen many peoples castigating the Prescott compared to
    the Northwood P4. We had a stretch of rainy days, so I tested
    some old PCs - I had a draw full of Pentium IVs to swap in them.
    One benchmark for L1 latency came out thus:
    Northwood 2 cycles
    Prescott 5 cycles
    Cedar Mill 4 cycles
    How did Intel bugger up the L1 cache?
    Anne Onime, Apr 6, 2011
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  2. Anne Onime

    Yousuf Khan Guest

    Thinking back to my ancient history, it had to do with the fact that
    Intel was aiming for 10GHz back then, so they stretched the instruction
    pipeline stage on the newer P4's, and this affected their latency.
    Higher latency in exchange for higher throughput. They expected that the
    greater clock rate would make up for the increased relative latency, by
    keeping the absolute latency the same.

    Yousuf Khan
    Yousuf Khan, Apr 7, 2011
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  3. Anne Onime

    Jim Guest

    Usually bigger the cache the slower the cache.
    Northwood's L1 data cache is 8KB Prescott's is 16KB.
    Jim, Apr 7, 2011
  4. Anne Onime

    Robert Myers Guest

    In order to get a really knowledgeable answer to this question, you
    should ask it in comp.arch.

    In order *really* to understand the difficulty and criticality of L1
    latency trades, I think you'd actually have to design a microprocessor,
    something that most of us will never get a chance to do, except possibly
    as a homebrew toy project.

    Robert Myers, Apr 10, 2011
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