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How do I load Instructions into Instruction Cache for mpc8248

Discussion in 'Embedded' started by damnc, Dec 2, 2004.

  1. damnc

    damnc Guest

    The manual from Motorola says...
    ************************
    The code that prefetches must be in cache-inhibited memory as in the
    following example:
    # Assuming interrupts are turned off, cache has been flushed,
    # the MMU is on, and we are executing in a cache-inhibited
    # location in memory
    # LR and r6 = Starting address of code to lock
    # CTR = Number of cache blocks to lock
    # r2 = nonzero numerator and denominator
    # ÔloopÕ must begin on an 8-byte boundary to ensure that
    # the divw and beqlr+ are fetched on the same cycle.
    ..orig 0xFFF04000
    loop: divw. r2, r2, r2 # LONG divide w/ nonzero result
    beqlr+ # Cause the prefetch to happen
    addi r6, r6, 32 # Find next block to prefetch
    mtlr r6 # set the next block
    bdnz- loop # Decrement the counter and
    # branch if CTR != 0
    ************************
    Q: Where do i load my code start address ..into LTR..where is that??
    Q: What is the size of each cache block? aand where do i load that?

    Thanks
     
    damnc, Dec 2, 2004
    #1
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  2. (damnc) wrote in
    Which manual? Which chip?
    Cache line (block) size will be specified in the User's Manual. You might
    a a bit more detail, like the CPU model number and some more descriptive
    text as to what you wish to do. Also, don't forget that this might be
    better asked in comp.sys.powerpc.tech. Follow-ups set.
     
    Mark A. Odell, Dec 2, 2004
    #2
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