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I2C Module and SMBus Receiving Slave

Discussion in 'Embedded' started by jalp.blanchard, Nov 4, 2005.

  1. An SMBus receiving slave may indicate reception of invalid command or
    data by using the NACK mechanism. My understanding is that most I2C
    module sequence is to immediately generate the NACK or ACK based on a
    bit setting in the I2C control register when you read the I2C module
    data register. The preferred sequence would be to stretch the clock,
    read the command/data byte, check if it is a valid command/data, set
    the SDA line and then release SCL. Is there a micro-controller I2C
    module that implements this feature or do I have to use bit-banging
    jalp.blanchard, Nov 4, 2005
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