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If I got this from running modelsim: written by continuous and procedural assignments

Discussion in 'Hardware' started by justalittle, Sep 23, 2012.

  1. justalittle

    justalittle Guest

    Hi,

    I'm learning systemverilog. And during the testbench-part, I got this from running modelsim: "written by continuous and procedural assignments"

    What kind of error did I make?
    And how can I correct it?
    Thanks
     
    justalittle, Sep 23, 2012
    #1
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