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Intel HEX format: extended segment address

Discussion in 'Embedded' started by eliben, Aug 22, 2008.

  1. eliben

    eliben Guest

    Hello,
    I have to implement a reader for the Intel HEX format, and there's
    something unclear in section 4 of the specification (Extended Segment
    Address Record).
    USBA is 16 bits, specifying bits 4-19 of the SBA. Later it says that
    the SBA defines a 64K segment, but it has only 4 low bits missing, not
    16, so its resolution is as low as 16 bytes instead of 64K ?
    This is while each data field offset is in fact 16-bit and can address
    inside 64K.
    So can there be an overlap between different records into the same SBA-
    defined segments ?

    In the Extended Linear Address Record it all works out because ULBA
    spoecified the upper 16 bits, so the data field offsets specify the
    lower 16.

    Eli
     
    eliben, Aug 22, 2008
    #1
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  2. eliben

    Tauno Voipio Guest


    You're right. There are 4096 combinations addressing
    the same address, if the carry from the top bit is
    ignored.

    The bits 4-19 specification comes directly from the
    8086 hardware model. The hex format was initially
    known as 8086 hex.
     
    Tauno Voipio, Aug 22, 2008
    #2
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  3. eliben

    eliben Guest

    Thanks and I have a folloup question. In the same 'extended segment
    format', how do CS and IP join to make the start address ? Is it just
    CS << 16 + IP ?
     
    eliben, Aug 23, 2008
    #3
  4. eliben

    Tauno Voipio Guest

    Yes.
     
    Tauno Voipio, Aug 23, 2008
    #4
  5. eliben

    eliben Guest

    Thanks a lot !
     
    eliben, Aug 23, 2008
    #5
  6. eliben

    Coos Haak Guest

    eliben wrote:

    CS << 4 + IP ;-)

    CS << 16 would make a 4 GB address on a CPU with 20 address bits.
     
    Coos Haak, Aug 23, 2008
    #6
  7. eliben

    eliben Guest

    Oh, I see. Any good online reference on this topic ?
    Searching Google for Intel, CS and IP doesn't bring much
     
    eliben, Aug 24, 2008
    #7
  8. eliben

    rickman Guest

    I don't know about Intel Hex, but I know that there are no Intel
    processors with a 20 bit address bus that use the Extended address
    format. 20 bits is only 1 MB. The 80286 used the segment registers
    to extend the address range of the 8086 to 20 bits. The 80286
    extended this further to 32 bits. The 386 chips may not have brought
    out all 32 address bits, but there was a full 32 bit (4 GB) address
    range and it was up to the designer to decide how the software address
    would be mapped to the hardware address.

    So I think Tauno was right, CS << 16 + IP.

    Rick
     
    rickman, Aug 24, 2008
    #8
  9. eliben

    Tauno Voipio Guest

    Sorry, Eliben is right - I did not look well enough.

    The addresses in 8086 hex are in 80x86 real mode segment:eek:ffset
    format, where the segment value is multiplied by 16 (shifted
    left 4) and added to the offset. In the basic 8086 architecture,
    the carry out of the bit 19 is lost, so the result loops back
    from 1 MByte to zero.
     
    Tauno Voipio, Aug 24, 2008
    #9
  10. eliben

    John B Guest

    www.xess.com/faq/intelhex.pdf
     
    John B, Aug 24, 2008
    #10
  11. eliben

    Coos Haak Guest

    24 bits.
    But the segments were still 64 Kb like the 8086. The segment registers
    were called selector registers in protected mode where the addressing
    was quite different from the real mode of the 80286 == native mode
    8086.
    Another protected mode, somewhat different of the 286 (24 bits).
    No. CS:IP in protected mode is different, like I said.
    Have a look at Intel documentation.
     
    Coos Haak, Aug 25, 2008
    #11
  12. eliben

    rickman Guest

    Opps, I meant the 80386 extended this further to 32 bits.
     
    rickman, Aug 25, 2008
    #12
  13. eliben

    rickman Guest

    Opps, no, I was right the first time... I can't read my own
    handwriting even when it is on the PC!
     
    rickman, Aug 25, 2008
    #13
  14. eliben

    eliben Guest

    I'm now reading and re-reading this branch of the thread, and still
    can't figure out how to treat the 4-byte value specifying CS:IP in
    record type 03 of the Intel format.

    CS << 4 + IP ?

    Or is the shift by 16 ?
    I'm more inclined towards shift by 4, because section 7 of the
    specification says:

    "Note that this record only specifies the code address within the 20-
    bit segmented address space of the 8086/80186."

    So it appears only real mode addressing (of 8086/80186) is specified.

    Eli
     
    eliben, Aug 30, 2008
    #14
  15. eliben

    John B Guest

    In which case you haven't bothered to read the intel spec in the link I
    gave you last week. Record type 3 is an Extended Segment Record. Here
    is an extract from the real Intel spec:

    The 16-bit Extended Segment Address Record is used to specify bits
    4->19 of the Segment Base Address (SBA), where bits 0->3 of the SBA are
    zero. Bits 4->19 of the SBA are referred to as the Upper Segment Base
    Address (USBA). The absolute memory address of a content byte in a
    subsequent Data Record is obtained by adding the SBA to an offset
    calculated by adding the LOAD OFFSET field of the containing Data
    Record to the index of the byte in the Data Record (0, 1, 2, ... n).
    This offset addition is done modulo 64K (i. e., 16- bits), ignoring any
    carry, so that offset wraparound loading (from OFFFFH to OOOOOH)
    results in wrapping around from the end to the beginning of the 64K
    segment defined by the SBA.

    So record type 3 is shifted by 4 bits.
     
    John B, Aug 30, 2008
    #15
  16. eliben

    eliben Guest

    John,

    1. First of all, I'm *really* thankful for your "giving me" the link
    to the Intel HEX spec, even though my initial post referred to a
    specific chapter from it (making the assumption that I wasn't aware of
    its existence weird).

    2. """In which case you haven't bothered to read the intel spec in the
    link I
    gave you last week. Record type 3 is an Extended Segment Record. Here
    is an extract from the real Intel spec:"""

    I wonder if you "have bothered" ? Record type 03 is "Start segment
    address record", not "Extended Segment Record" (type 02).

    3. You've misunderstood my question (I asked about the start address,
    namely the CS:IP registers) and quoted a whole section of the spec
    I've basically memorized by now (but oh, the section doesn't even
    mention what I asked about).

    Anyway, to set the record straight. There are two issues here, the one
    dealing with offset specification (type 02), which Jack Klein cleared
    in his post, and the other with the start address (type 03), which is
    still unclear (see the thread of replies by Coos Haak, rickman and
    Tauno Voipio).

    --

    P.S: Pardon for being cynical, this is in no way personal. But if you
    have no way to help, *please* just don't bother replying. Really, you
    don't have to ! Especially when your reply is rude and condescending
    (and wrong at the same time, how embarrassing).

    Eli
     
    eliben, Aug 31, 2008
    #16
  17. eliben

    Tauno Voipio Guest

    OK - I'll attempt to repair my previous blunder:

    The values in record type 3 are real-mode 80x86 code
    segment and instruction pointer (CS:IP). As in all
    real mode segmentation, the segment register value
    is multiplied by the paragraph size (= 16 bytes)
    and added to the offset component. So, the two
    16 bit values are combined: ((cs << 4) + ip) % 1048576.

    The modulo operation comes from the 8086 (and -186),
    where there are only 20 address lines. In 80286 and
    newer, the modulo operation is not there, so it is
    possible to address nearly 64 kibytes over the one
    megabyte limit. This is why there is the A20 gate
    in the PC/AT design - for compatibility with the
    basic PC and PC/XT.
     
    Tauno Voipio, Sep 1, 2008
    #17
  18. eliben

    eliben Guest

    Thanks. This clears things up.

    Eli
     
    eliben, Sep 1, 2008
    #18
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