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large FIFO buffer

Discussion in 'Embedded' started by Adam Kumpf, Mar 13, 2005.

  1. Adam Kumpf

    Adam Kumpf Guest

    Hello all,

    I am in the middle of laying out a design for a medical device the reads
    in data pretty quickly (~20MHz) in bursts, but is limited to a slow serial
    connection to transfer the data. The solution that comes to my mind is a
    large FIFO buffer (~100k+) that can take an 8-bit parallel input, but I
    can't find them anywhere in a reasonable price range. I've looked all over
    at the common manufactures of logic devices (TI,nationalsemi) and some
    distributors (digikey,mouser) but can't find much. I hear of hard drives
    with 512k buffers/caches quite commonly. what am I missing here?

    Does anyone know of a model/part# of a pretty high speed, 100k+ fifo

    Thanks in advance for your help.

    Best Regards,
    Adam Kumpf

    Adam Kumpf, Mar 13, 2005
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  2. Adam Kumpf

    Uwe Bonnes Guest

    20 MHz is not really high speed...

    Get some fast SRAM and a CPLD/FPGA and do the FIFO by hand. There are
    Cypress Dual port memory available, but they are normally hard to get in low
    quantities. Well, digikey carries Cy7C009/019, but with a real proce tag...

    Uwe Bonnes, Mar 13, 2005
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  3. Adam Kumpf

    ktbowman Guest

    I agree you want to use an FPGA for this solution.
    Would be very simple. If you're doing research might
    look for A/D conversions as they are usually clocked
    into a FIFO for holding before processing.

    Terry Bowman
    ktbowman, Mar 13, 2005
  4. On Sunday, in article
    What is reasonable price range??
    Often these caches are SRAM/DRAM based using some of the memory of the
    hard drive or directly under ASIC control.
    20MHz is not high speed for FIFOs consider looking at IDT (www.idt.com)
    for their synchronous and asynchronous devices. I do assume this burst data
    has some form of clock with it.

    Has someone else has said a 1Mb(128KB) or 4Mb(512KB) SRAM part is easy to
    find and a PLD/FPGA to drive that will be fairly trivial. Especially as the
    output is slower and by the sounds of things could have its read delayed
    (registered), if necessary whilst in the middle of a write cycle.
    Paul Carpenter, Mar 13, 2005
  5. Adam Kumpf

    Adam Kumpf Guest

    Thanks for all of your help. The SRAM decision only slightly complicated
    the design, but reduces the price drastically(by a factor of 10 or more!)...
    just what I was looking for! :)

    I'll have a microcontroller on board, so maybe I can bypass the CPLD/FPGA if
    I'm clever.

    Thanks again.

    Best Regards,
    Adam Kumpf
    Adam Kumpf, Mar 13, 2005
  6. Adam Kumpf

    Tom Woodrow Guest

    Tom Woodrow, Mar 14, 2005
  7. Adam Kumpf

    ktbowman Guest

    Be careful trying to use the processor to do the same task as the FPGA
    described above. AN FPGA will typically have no latencey or delay
    in servicing the output and stuffing the FIFO. These delays are often
    times not guaranteed w/ a processor. If your processor can be doing
    anything else, which is likely, make certain it will get the data
    the next piece of data is ready. This all depends on the context
    latency of your processor (worse case) versus the data input speed.

    Also, an FPGA could be used without SRAM in some cases depending on
    the size and depth of the data. This also depnds on the FPGA/CPLD used
    as well. If this is possible then it could be cheaper then using SRAM
    if the FPGA can used for other purposes.

    Terry Bowman
    ktbowman, Mar 14, 2005
  8. Adam Kumpf

    Joe.G Guest

    Joe.G, Mar 22, 2005
  9. Adam Kumpf

    Tom Woodrow Guest

    Tom Woodrow, Mar 22, 2005
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