M2N32 WS professional and 4x1GB: Solved?

Discussion in 'Asus' started by Arno Wagner, Jan 13, 2008.

  1. Arno Wagner

    Arno Wagner Guest

    Dear all.

    I recently bought a second Kingston KVR800D2E5K2/2G module set. These
    are DDR2 CL5 ECC unbufferd CL5 modules and are not on the officiall
    list for 4 modules or at all. This is with BIOS 1501.

    Of course, inserting all 4 modules the system did hang before the BIOS
    posted anything to screen. Apparently this is an issue other people
    have run into as well. I then put one module form each pair in the
    first two slots to test whether the modules were incompatible
    (Kingston uses different chips, but usually makes sure they have the
    same timing and eeprom settings), and this worked,confirming that the
    modules were not at fault. Looking through the details of the memory
    configuration in the BIOS, I found something strange in
    Advanced->CPU-config->DRAM config->Advanced Memory Settings:

    "CPU on die termination" was set to 300R, which is ok for 1 module,
    but not 2 or 4. Also "DRAM termination" was set to disable, which is
    problematic. Setting the CPU termination to "auto" did not
    help. Setting it to 75R and setting DRAM termination to either auto or
    50R did produce a working system, with 4GB available, that passes my
    initial memory tests.

    Analysis: What happened here? The values I found are those set by the
    BIOS initially, I never touched them. Hovever 300R CPU termination and
    DRAM termination disabled are the most conservative settings and
    should work with about any single (!) module. With two modules it
    already is a question of luck. I had one pair of Corsair Twin-X CL4
    2x1GB RAM before, that produced a very hard to find bit-error
    occasionally when both modules were installed. I speculate that with
    the proper settings here (150R CPU termination and DRAM termination
    100R for two modules) the Corsair memory would actually have worked
    fine. Since I got a warranty replacement, I cannot test that anymore.

    Now, why these settings? I think memory configuration works as
    follows: If the modules are recognized form a BIOS-internal list,
    optimal settings are used. If not, the most conservative settings are
    used. These are fine for one module, borderline for two modules and
    fail for 4 modules. It is to Kingston's credit that a pair of their
    modules have enough reserves to work fine with the settings for one
    module. It is also not surprising that a 4 module configuration fails
    with the default settings.

    In addition, the reason for the failure is entirely obvious: Each
    module puts a capacitive load on the signal lines. This, multiplied by
    the termination resistance (300R,150R or 75R on CPU side and 200R,
    100R and 50R on the DRAM side) gives the signal delay on the signal
    lines (as first approximation). Putting a capacitive load four times
    as high as the termination allows, just delays the signals too
    much. Not having termination on the DRAM side produces signal echos,
    that, again, are no issue for one module, may still be low enough for
    two modules and causes the RAM to fail for 4 modules.

    Some people seem to have had success with raising DIMM voltage. This
    basically makes the memory faster and the signals stronger and
    partially compensates for the signal delay problem. But it does solve
    the wrong problem and it does not adress the echo issues, which can be
    the reason for crashes when this approach is used.

    Summary: When you use memory not on Asus's list, set your own
    parameters. With 2 modules it may be a good idea to set the "CPU on
    die termination" manually to 150R and the "DRAM termination" to
    100R. With 4 modules you should set the "CPU on die termination" to
    75R" and the "DRAM termination" to 50R. (The settings for 4 modules
    also work with two modules, so you can actually access the BIOS to set
    them with just two modules installed.) Do not increase DIMM voltage,
    it may shorten the life expectancy of your memory.

    Disclaimer: This is something I found out some hours ago. If I run
    into problems, I will post them here. Also, my statements about what
    the right termination is are speculative, since I did not find the CPU
    manual for mine (x2 5600+) on AMD's website.

    Arno Wagner, Jan 13, 2008
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  2. Arno Wagner

    Paul Guest

    You are right. ODT has to be set in an appropriate way for the channel
    configuration. One or two DIMMs in the channel, requires different
    termination settings.

    I also wouldn't try to rationalize the results, as it is a lot more
    complicated than R*C. There is a document here which describes the
    different settings appropriate for one or four banks. In this
    description, the "controller" would be the Northbridge.


    This document shows waveshape as a function of various scenarios.
    Degradation of waveshape (reduction in eye opening) is more likely
    to be a result of bad termination choices for each test case. And
    eye opening is one factor in proper sampling of data.


    Paul, Jan 13, 2008
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  3. Arno Wagner

    Arno Wagner Guest

    I know. I included that rationalisation in order to have a simple
    and still somewhat accurate one, instead of having no explanation
    at all. I don't like technical fixes that require you to believe in
    some specific "black magic". Better a partial explanation than none
    at all.
    Very good references. Highly recommended for anybody that wants
    to understand what is going on in detail. Both do require
    significant EE knoledge though.

    Arno Wagner, Jan 13, 2008
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