1. This forum section is a read-only archive which contains old newsgroup posts. If you wish to post a query, please do so in one of our main forum sections (here). This way you will get a faster, better response from the members on Motherboard Point.

Memory Latency Technical Specifications

Discussion in 'Motherboards' started by pg, Jan 12, 2008.

  1. pg

    pg Guest

    al cl wl rl bl ddr ddr2 ddr3 ... RL = AL + CL / WL = RL -1 ...

    It years past, when SDRAM was all we had, memory latency was quoted
    with the CL figure - CL2 was supposed to be better than CL3

    Nowadays, with DDR2, DDR3 and even DDR4 flooding the markets, memory
    latency specs, to me at least, suddenly exploded !

    CL is not enough, now they have al cl wl rl bl and in one of the
    search listing that I found, from ieee.org, they even have this
    formula ---- RL = AL + CL / WL = RL -1 ...

    Now my head starts to ache.

    Can anyone here please enlighten me, in plain everyday English words,
    what all those things stand for? What are their significants? How does
    that effect the memory performance ?

    Please help !

    Thank you !
     
    pg, Jan 12, 2008
    #1
    1. Advertisements

  2. pg

    MitchAlsup Guest

    AL address latency. After sending one address this is the number of
    cycles one muust delay a second address before sending.
    WL write latency. This is the number of cycles after a write has been
    started before you are allowed to deselect that bank.
    CL command latency.

    What is going on is that the external interface is getting faster, but
    the internal arrays are not. So back in SDRAM days these were all 1
    (or smaller) and since you could only do one thing per cyle on the
    pins, all was good (e.g. invisible).

    When a bank is selected (ACTIVATE) there is an power surge from firing
    all of the bank decoders, the word line driver, all of the bank sense
    amps, and then a time is needed for the sense amps to re-establish the
    stored DRAM cell charge. At the same time there are various goings on
    over at the pins also causing minor surges. You really do not want the
    power to be surging at the moment when the sense amp fires! (hint:
    sense amps read the wrong data) When the time between requests was 12
    ns all of this was hidden, at 8-ish ns it showed up as an additional
    cycle, but since the very vast majority of controlers were doing line
    reads/writes, it remained invisible (through DDR 2). Now we are
    entering the realm where the surge can last longer than the transmit
    time of a line. So inorder to make DRAM reliable, one has to avoid
    doing analog-ish-like things during these current surges. Another way
    to address the problem would be to dedicate more DRAM pins for power
    and ground, but the industry is not going that direction due to their
    cost-driven basis (pins cost real money and power routing might add
    another layer of metal to the part).

    WL This is the latency for write data to actually get into the DRAM
    storage cell and allow that bank to enter a precharge state. You
    really do not want the data only to get to the sense amp and then de-
    select a bank, because it is unclear if the data has made it to the
    DRAM cell or not.

    Mitch
     
    MitchAlsup, Jan 13, 2008
    #2
    1. Advertisements

  3. pg

    Mellowed Guest

    AL address latency. After sending one address this is the number of
    cycles one muust delay a second address before sending.
    WL write latency. This is the number of cycles after a write has been
    started before you are allowed to deselect that bank.
    CL command latency.

    What is going on is that the external interface is getting faster, but
    the internal arrays are not. So back in SDRAM days these were all 1
    (or smaller) and since you could only do one thing per cyle on the
    pins, all was good (e.g. invisible).

    When a bank is selected (ACTIVATE) there is an power surge from firing
    all of the bank decoders, the word line driver, all of the bank sense
    amps, and then a time is needed for the sense amps to re-establish the
    stored DRAM cell charge. At the same time there are various goings on
    over at the pins also causing minor surges. You really do not want the
    power to be surging at the moment when the sense amp fires! (hint:
    sense amps read the wrong data) When the time between requests was 12
    ns all of this was hidden, at 8-ish ns it showed up as an additional
    cycle, but since the very vast majority of controlers were doing line
    reads/writes, it remained invisible (through DDR 2). Now we are
    entering the realm where the surge can last longer than the transmit
    time of a line. So inorder to make DRAM reliable, one has to avoid
    doing analog-ish-like things during these current surges. Another way
    to address the problem would be to dedicate more DRAM pins for power
    and ground, but the industry is not going that direction due to their
    cost-driven basis (pins cost real money and power routing might add
    another layer of metal to the part).

    WL This is the latency for write data to actually get into the DRAM
    storage cell and allow that bank to enter a precharge state. You
    really do not want the data only to get to the sense amp and then de-
    select a bank, because it is unclear if the data has made it to the
    DRAM cell or not.

    Mitch

    Many thanks for such a clear response. We all got educated.
     
    Mellowed, Jan 14, 2008
    #3
  4. pg

    daytripper Guest

    Almost all ;-)

    "Re-establishing" read data back into the array actually happens at the end of
    the read operation, not the beginning or middle of the read. This also marks
    the beginning of the "pre-charge" duration that follows the end of the read
    operation, similar to what happens when a write is committed to the array...

    Cheers

    /daytripper
     
    daytripper, Jan 14, 2008
    #4
    1. Advertisements

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.