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Mixing address lines in SDRAM.

Discussion in 'Embedded' started by Wlad, Jul 9, 2004.

  1. Wlad

    Wlad Guest

    Dear all,

    I have to boot-up a device based on Hitachi uP with external SDRAM
    (2x256Mb). The device was designed by somebody else and I only have to
    get it working. However there is something that bothers me very much.
    Probably to easen PCB layout the designer has mixed data and address
    lines for SDRAM: i.e. pin D0 of SDRAM is connected to pin D7 of uP. All
    other interface signals (RAS#,CAS#,CLK,CKE,UDQM,LDQM,WE#,CE#) are
    connected correctly. While mixing data lines seems ok to me (let me know
    if I'm wrong) mixing address lines looks unacceptable.
    Here are the connections:

    SDRAM uP
    ------------------
    A0 A5
    A1 A4
    A2 A3
    A3 A2
    A4 A14
    A5 A13
    A6 A12
    A7 A11
    A8 A10
    A9 A9
    A10 A6
    A11 A8
    A12 A7

    BA0 A15 (bank select)
    BA1 A16 (bank select)

    Will this connection work? For the time being I know that I must forget
    burst transfers. Are there any obstacles for SDRAM in this configuration
    to work with 1-byte burst transfers?

    Thanks
    Wlad
     
    Wlad, Jul 9, 2004
    #1
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  2. Wlad

    Karl Olsen Guest

    In

    I think it should work, but be careful when you configure the SDRAM mode
    register which uses the SDRAM address lines for the configuration bits.

    Karl Olsen
     
    Karl Olsen, Jul 9, 2004
    #2
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  3. It looks a bit weird, but you'll have to consult the datasheet of the
    CPU. Address lines of SDRAMs are multiplexed, so it is all a question
    of which row and which column address is output at which CPU address
    pin at what time. It might be that the connections are right. After
    all, the one who designed the board, must have considered that. If he
    had no idea of what he was doing, he would probably not have got as
    far as finishing a board. And if the connection is right, then it will
    support burst transfers if the CPU supports them. Like you, I can't
    see any problems with the data bus (even though I never tried that).

    Michael
     
    Michael Kr?mer, Jul 9, 2004
    #3
  4. Wlad

    Rick Merrill Guest

    It would be worth the time to track them down, if alive, and ask. - RM
     
    Rick Merrill, Jul 9, 2004
    #4
  5. The connection scheme really seems a little bit weird. While address
    Interchanging is ok for SRAM, for SDRAM (and asyn. DRAM) it can be a problem.
    In your example, low address lines of the µP are connected to the higher lines
    of the RAM such that when the µP outputs a column address on the lower eight or
    nine lines, the RAM gets some of them on its higher address inputs A9...A12
    where it doesn't expect them.
    Furthermore, SDRAMs use input A10 as part of the command word to switch on and
    off AutoPrecharge. Simultaneously with the column address on the lower address
    lines command Bit 'AP' is sampled from A10.
    Unless the SDRAM controller of your µP (for some mystic reasons) uses a
    non-standard address pattern (i.e. outputting AP on address line A6 while column
    address is on lines A5..2,A14..10) or the SDRAM chips are a little bit
    'non-standard', your design probably will not work.

    HTH,
    Jens
     
    Jens Hildebrandt, Jul 9, 2004
    #5
  6. Well, if he's alive, track him down to take him down ;)

    I have serious doubts ! Unless you have very special SDRAM and/or a very flexible SDRAM controller (like a FPGA;)), I don't possibly see how it could work. Maybe by disabling completly burst and if your SDRAM controller can put precharge on AD6 you can exchange single word at a time but that's a lot of wasted bw IMHO.

    At least on the uC and SDRAM I've seen so far, it won't work at all.


    Have you actually seen it boot once ?


    Sylvain Munaut
     
    Sylvain Munaut, Jul 10, 2004
    #6
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