Nf7s v2.0 and Mobile Athlon: more stable at lower Vcore?

Discussion in 'Abit' started by Doug, Aug 18, 2005.

  1. Doug

    Doug Guest

    In overclocking my Mobile Athlon my former tactic was to start from the
    highest Vcore and work my way down. I've just noticed that above 1.9V Vcore
    my Mobile Athlon is very unstable and that at 1.875V it seems most stable. I
    even got the system to boot and run memtest at 230*11.5 = 2645, which I
    could never get at higher voltages.

    I also want to mention my Patriot Extreme Performance Low latency memory
    which enabled me to get to 230Mhz FSB/memory synched. My Kingston Hyperx
    could never get anywhere close to 230Mhz. Patriot gets a thumbs up from me.
    Doug, Aug 18, 2005
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  2. Doug

    - HAL9000 Guest

    Here is a WAG...

    The cpu logic voltages must be translated to larger voltages outside
    the cpu (amplification). Increasing the vcore voltages (beyond design
    limits) may interfere with the voltage translation process. The
    performance of the process is/can be influenced by noise. Noise
    increases as you increase vcore.


    Motherboard Help By HAL web site:
    - HAL9000, Aug 18, 2005
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  3. Doug

    Doug Guest

    Uh, right. Ever worked with MOSFET transistors Forrest? Obviously not.
    Nothing like spouting a bunch of crap when you have no idea what you're
    talking about. Putz.
    Doug, Aug 19, 2005
  4. Doug

    - HAL9000 Guest

    You'll need to do better.
    - HAL9000, Aug 19, 2005
  5. Doug

    acc7 Guest

    Your apporach to selecting the voltages is actually backwards. Your
    components will survive better if you run them at the lowest heat
    disapation conditions you can. That means never use any more voltage
    than you need for stability. Additionally your mobile XP's were
    designed to run at the lower voltages.

    Hence I suggest changing your approach and start with much lower
    voltages. My XP mobiles will OC at 40% to 55% at voltages around
    1.575 to 1.65 Vcore.

    In your other post you asked about Super PI as a test for your OC.
    Itr is a quick way to see what the max you'll get. And it cang ive
    you some bragging rights. Hoiwever, other than giving a quick test it
    is not worth much. You can push some pretty high OC's thru the Super
    PI test that will never be really stable for you. 4-24 hours on
    Prime95 torture test will give a better measure of stability.

    Hope this helps some.
    acc7, Aug 20, 2005
  6. Doug

    Doug Guest

    And you'll need to prove your BS assertion that increases Vcore increases
    noise. Let's see some proof. I've worked w/MOSFET's and BJT's have you
    Doug, Aug 21, 2005
  7. Doug

    Bill Guest

    You are a pricky little turnip, aren't you?

    Bill, Aug 21, 2005
  8. Doug

    Doug Guest

    I call BS on this one HAL (or whatever the **** your real name is). Let's
    look at some real-world gain equations for CMOS amplifiers:

    For a CMOS amplifier consisting of three transistors where Q2 and Q3 are a
    matched pair of p-channel devices connected as a current mirror that is fed
    w/a reference DC current Iref and Q2 behaves as a current source. Q2 will be
    in pinch-off when the voltage at its drain is lower than its source (Vdd) by
    at least (Vsg - |Vip|) where Vsg is the DC bias voltage corresponding to a
    drain current of Iref. When in pinch-off, Q2 has a high output resistance
    ro2 where:

    ro2 = |VA|/Iref.

    Transistor Q2 is used as the load resistance for the amplifying transistor
    Q1 and is called an active load. It follows that when Q1 is operating in
    pinch-off, the small signal voltage gain will be equal to gm1 multiplied by
    the total resistance between the output (vo) and groung, which is (ro2 ||
    ro2). Thus a large gain is obtained in the CMOS amplifier. The voltage gain
    is inversely proportional to to the square root of the bias current:

    Av = - (((Kn^0.5) * |Va|)) / (Iref^0.5)). Vdd is therefore irrelevant to
    gain, which includes noise. As a matter of fact ignorant asshole,
    the noise margins of CMOS devices INCREASE w/increasing Vdd as any datasheet
    will prove. Motorola specifies for standard CMOS logic (0.1Vdd):

    Vdd = 5V, for which the worst-case noise margins are Nml = Nmh = 0.5V
    Vdd = 10V, for which the worst-case noise margins are Nml = Nmh = 1 V
    Vdd = 15V, for which the worst-case noise margins are Nml = Nmh = 1.5V

    Time to go back to school dickhead. I guess your MCSE, Network+ and A+
    didn't teach you anything about circuit analysis or basic transistor theory.
    Doug, Sep 9, 2005
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