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PCI Addressing

Discussion in 'Embedded' started by saju.nair.m, Jun 20, 2007.

  1. saju.nair.m

    saju.nair.m Guest

    I am a novice user and hence please excuse if the question is too

    I have a question regarding the address that a PCI device should use
    when it "initiates" a transaction.

    Host <--------> Device

    The host configures the device during the initial boot-up time and
    the host maps the device to its memory map (ie the Device's BARs get
    programmed). So, any future accesses initiated by the Host will use
    the appropriate address.

    However, if the Device (assume an intelligent device card containing
    a processor) wishes to perform an access on the PCI bus, how does it
    figure out what address to drive on the PCI_AD[31:0] bus ?

    Is it implementation specific ?

    - Saju
    saju.nair.m, Jun 20, 2007
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  2. saju.nair.m

    Zara Guest

    No, it depends on how the device is programmed. It should have some
    configuration register where you put the address fro such
    transacitions, or a pointer to this address, or to a strcuture to this
    address, or... It is device specific, but the processor is reponsible
    of feeding that address to the devioce.

    best regards,

    Zara, Jun 20, 2007
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  3. Generally a PCI device won't master the bus (initiate a transaction) until
    it has been configured by software (application/driver) on the host.

    An example would be a PCI card with a DMA engine - the application or
    driver on the PC would configure the address of a memory buffer in PC host
    memory in a register on the card before the DMA commences.

    AFAIK there are no 'well known' addresses in PCI space so there's no way a
    device could initiate a transfer without being configured with an address

    Mark McDougall, Jun 20, 2007
  4. There are "several" layers of address translation
    involved. Let's skip the MMU and just deal with
    physical addresses :)

    The host processor sees the PCI address space through
    a window whose physical base address is located by
    system specific means at some fixed physical address.
    Any physical address to this range initiates a PCI
    bus access cycle.

    The PCI host adapter contains a set of registers that
    specify the translation of physical addresses
    from the host processor (the window) to PCI address
    range. This range of addresses actually goes onto
    the PCI bus. But wait! There's more.

    The BAR's that you refer to, are in the PCI slave/device
    adapter. These are setup at bus enumeration time with
    the PCI address range that the device will respond too.

    If the PCI slave device contains shared memory on its
    local bus that is visible to PCI bus masters, there
    may be yet another translation to the device's internal
    memory map.

    I've conveniently left out the issue of PCI bridges ;-)
    (and probably some other stuff)

    Michael N. Moran (h) 770 516 7918
    5009 Old Field Ct. (c) 678 521 5460
    Kennesaw, GA, USA 30144 http://mnmoran.org

    "So often times it happens, that we live our lives in chains
    and we never even know we have the key."
    The Eagles, "Already Gone"

    The Beatles were wrong: 1 & 1 & 1 is 1
    Michael N. Moran, Jun 20, 2007
  5. saju.nair.m

    saju.nair.m Guest

    Hi Mark,
    Thanks a lot for your response.
    To summarize, if a device needs to initiate an access
    (through a DMA engine -or- possibly by a processor on the device
    card), then,
    the host s/w needs to configure some implementation-specific
    registers in
    the device that will provide the valid PCI address that is accessible
    by this

    - Saju.

    saju.nair.m, Jun 21, 2007
  6. Generally, yes.

    Mark McDougall, Jun 21, 2007
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