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Probelms simulating Xilinx FFT version 3.2 core in ModelSim SE

Discussion in 'Embedded' started by makhan, Apr 11, 2008.

  1. makhan

    makhan Guest

    Hello,

    I am using Xilinx 9.1i and Modelsim 5.7g. I instantiated a coregen
    module for FFT ver 3.2. After successfully synthesizing the module
    with the generated xco, I am now trying to simulate the module. The
    hierarchy is as follows:
    fft_tb => fft_top => fft.v (generated by coregen)

    I am using a custom script as follows:
    #############################################
    vlib work
    vlog fft.v "../fft_top.v" fft_tb.v
    vsim -t 1ps -L xilinxcorelib_ver -L unisims_ver -L simprims_ver -lib
    work fft_tb_v glbl
    view wave
    add wave *
    add wave /glbl/GSR
    do {fft_tb_v.udo}
    view structure
    view signals
    run 1000ns
    ##############################################
    I have compiled simprims, xilinxcorelib and unisim libraries (verilog
    versions) and added them to Modelsim. When I select Simulate
    Behavioral Model from Xilinx, it opens modelsim and finds all the
    xilinx primitives, which fft module calls, except for these:

    # ** Error: (vsim-3033) fft.v(10097): Instantiation of
    'fft_r22_cnt_ctrl_6' failed. The design unit was not found.
    # Region: /fft_tb_v/uut/U1
    # Searched libraries:
    # C:/Xilinx91i/verilog/mti_se/XilinxCoreLib_ver
    # C:/Xilinx91i/verilog/mti_se/unisims_ver
    # C:/Xilinx91i/verilog/mti_se/simprims_ver
    # work
    # ** Error: (vsim-3033) fft.v(10111): Instantiation of
    'fft_r22_cnt_ctrl_7' failed. The design unit was not found.
    # Region: /fft_tb_v/uut/U1
    # Searched libraries:
    # C:/Xilinx91i/verilog/mti_se/XilinxCoreLib_ver
    # C:/Xilinx91i/verilog/mti_se/unisims_ver
    # C:/Xilinx91i/verilog/mti_se/simprims_ver
    # work
    # ** Error: (vsim-3033) fft.v(10183): Instantiation of
    'fft_r22_cnt_ctrl_8' failed. The design unit was not found.
    # Region: /fft_tb_v/uut/U1
    # Searched libraries:
    # C:/Xilinx91i/verilog/mti_se/XilinxCoreLib_ver
    # C:/Xilinx91i/verilog/mti_se/unisims_ver
    # C:/Xilinx91i/verilog/mti_se/simprims_ver
    # work

    So I dont understand why these primitives are present in the core and
    why are they not subdivided into modules which are present in simprims
    library or any xilinx library for that matter.

    Is it a problem of using older Modelsim version with new xilinx
    version? Do I need to upgrade ips for 9.1, I am currently working with
    the ip set provided in xilinx installation?

    Any ideas how I can fix the problem?

    Thanks in advance

    Mansoor
     
    makhan, Apr 11, 2008
    #1
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  2. makhan

    makhan Guest

    I found a workaround, if the FFT core is generated with bit revered
    order instead of Natural Order, then the errors are removed and
    simulation runs smoothly.

    Mak
     
    makhan, Apr 11, 2008
    #2
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  3. makhan

    sprocket Guest

    ^^^^^^^^^^^

    Nuff respect?
     
    sprocket, Apr 11, 2008
    #3
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