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Re: reason for AMD's Bulldozer fiasco?

Discussion in 'Intel' started by Yousuf Khan, Oct 22, 2011.

  1. Yousuf Khan

    Yousuf Khan Guest

    I think the main difference is that the Interlagos Opteron chips are
    being used in servers where all of the cores make a difference, but the
    Zambezi desktop chips are being used in desktops and not fully utilized.
    Good for multithreaded workloads, not great on single-threads though.

    Yousuf Khan
    Yousuf Khan, Oct 22, 2011
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  2. Yousuf Khan

    Robert Myers Guest

    Apparently, AMD did too good a job selling its crippled "cores" as
    "cores." Currently, the Microsoft scheduler will just as willingly
    force two threads to share a common front end and FPU as to do the
    more sensible thing and push the busiest threads onto separate front
    ends and FPU's. Did no one at AMD check into that ahead of time? The
    problem, of course, is not unfixable. Bulldozer will still be an
    inferior product, but it won't be quite as disappointing for Windows,
    once the Windows scheduler is fixed to accommodate AMD's "cores."

    Robert Myers, Oct 30, 2011
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  3. Yousuf Khan

    Yousuf Khan Guest

    It probably explains why they fired their CEO, Dirk Meyer, early in the
    year so unexpectedly. There was no real reason ever given at the time,
    and that was a period of time when it looked like AMD was doing really
    well too, but we can now guess in hindsight. They were probably already
    aware of the problem back then.

    AMD is now showing off the processor running under Windows 8 beta with
    its newly designed scheduling system. It's showing some definite
    improvements, both minuscule and significant. So I don't know if this is
    an admission that Windows 7's scheduler will never be improved, or that
    the Windows 8 scheduler won't be backported to Windows 7.

    Another problem with the design seems to be that AMD designed their very
    own Pentium 4-concept processor. That is, it's highly pipelined,
    resulting in huge losses during branch misses, but also allowing it to
    be clocked extremely high. And much like the Pentium 4's of old, the
    performance never really took off until they were clocked really high.
    Also like the Pentium 4's, highly clocking them also result in huge
    power consumption.

    They are talking about bringing out a new stepping that won't result in
    better single-threaded performance, but in better power management. This
    would indicate to me that they trying to beef up the power mgmt, so that
    when they start clocking it really hard, then it won't be using any more
    power than it is now.

    Yousuf Khan
    Yousuf Khan, Oct 31, 2011
  4. Yousuf Khan

    Robert Myers Guest

    The enormously long pipeline wasn't the only distinguishing feature of
    NetBurst. According to someone I trust, parts of the NetBurst design
    ran at double-time. Thus, parts of the 3GHz processors were already
    running at 6GHz, thus explaining in part the enormous power
    consumption problem that NetBurst had. Unfortunately, not enough
    instructions would run on the faster pipeline to justify the design
    strategy, and Intel was caught between an unexpected rock and hard
    place. The original thought was to get a processor out with a label
    frequency in well in excess of 1GHz, leaving AMD in the dust. Known
    performance problems would be addressed by beefing up the faster
    pipeline. In fact, the needed transistors may well have been in the
    original NetBurst design and had to be thrown overboard because of the
    power envelope. Intel probably knew a long time ago that the real
    problem was power management. They just weren't as fast or as
    successful in fixing it as they thought they would be.

    Robert Myers, Nov 1, 2011
  5. Yousuf Khan

    Yousuf Khan Guest

    I think you're referring to the P4's floating point unit which was
    optimized for SSE2, but fell behind in regular x87 floating point.
    Interestingly, the new AMD Bulldozer floating point unit is expected to
    perform best in the newer AVX or 256-bit SSE instructions, rather than
    the older 128-bit SSE instructions.

    There were other doubled-speed interfaces like their FSB, which was
    running at 400MHz (eventually became 566MHz, I think), vs. AMD at
    200-266MHz, or P3 at 100-133MHz. That required the highest-speed Rambus
    or DDR memory to make good use of its bus.
    Which again seems to be the exact same problem that AMD will have to
    face with Bulldozer. Their next revision stepping is going to be
    entirely about getting the power consumption under control.

    I think AMD's biggest problem was not that Bulldozer has low IPC (it
    does), but that AMD couldn't right away bring Bulldozer out with enough
    clock frequency to compensate for its IPC. It's now got to really start
    pushing the clock speeds out.

    Yousuf Khan
    Yousuf Khan, Nov 3, 2011
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