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Relationship between PCLK and HCLK in AMBA system.

Discussion in 'Embedded' started by marcoa.castellon, Sep 22, 2006.

  1. Hello.

    I was wondering if someone can explain to me the relationship between
    the HCLK (AHB side) and PCLK (APB side) in an AMBA system.
    After the bridge, is the PCLK frequency the same as that of HCLK?
    How much slower is the APB side compared to the AHB side, or is it just
    at matter of the number of clock cycles required to perform the

    Do peripherals connected to the APB divide down PCLK when they are not
    required to operate at PCLK/HCLK frequency?

    Thank you in advance.
    marcoa.castellon, Sep 22, 2006
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  2. marcoa.castellon

    Mad I.D. Guest

    On 22 Sep 2006 10:28:38 -0700, wrote:

    AHB is a fast bus. APS is not because peripherals are slow.
    Clock for APB is AHP/(int)number.

    On my ARM system I can set APB clock as 1/4, 1/2 or 1/1 of AHP clock.

    Ivan from Croatia
    Mad I.D., Sep 22, 2006
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  3. marcoa.castellon

    Joseph Guest

    It depends on the system level design. In many SoC / ASICs the HCLK and
    PCLK are the same. However, there are some cases where PCLK is divided
    from HCLK. The design of the AHB to APB bus bridge will have to adapt
    to the design requirement. The implementation is the choice of system
    designers, not a part of AMBA specification.

    For example, if you are designing a new chip with an AHB clock frequency
    of 200MHz, and from timing analysis result you find that the APB cannot
    reach this speed, you can use a AHB to APB bridge that allow PCLK to be
    half of HCLK frequency, and run the PCLK at 100MHz.

    If a peripherals cannot operate at PCLK / HCLK frequency, they can be
    designed to support multiple clock domains. The bus interface can
    operate at PCLK frequency, and the rest of the peripheral operate at a
    slower frequency. Synchronisation logic will be needed between the
    different clock domain if they are not synchronous to each other. This
    is a rather complicated area in chip design and can go wrong easily if
    not handled carefully.

    Joseph, Sep 25, 2006
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