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SMT32F207 FSMC interfacing SJA1000, SRAM, Compact Flash

Discussion in 'Embedded' started by christoph531, Feb 14, 2012.

  1. christoph531

    christoph531 Guest

    Hello,

    I would like to use the STM32F207 in order to interface up to 8 ca
    channels by means of the SJA1000 can controller IC. In addition there i
    need for Compact Flash interface, plenty of external ram and flash memory
    The Flexible Static Memory Controller (FSMC) peripheral seems that it coul
    handle these requirements, but I'm not familiar with STM32 and so I hav
    some questions.

    First of all: Using the internal CAN controller of the STM32 or using th
    microchip MCP2515 with SPI interface is completely out of the question!
    really need 8 highspeed CAN channels with parallel interface to ensure hig
    data throughput.

    1) Does the SJA1000 fit to the FSMC? The FSMC would have to suppor
    multiplexed data/address lines in 8 bit datawidth mode. In that case, ca
    the more significant adresslines (A8 - A10) be used to select one of the
    can controller (with some additional hardware), or are these adress signa
    not present on the bus regarding to the multiplexed mode?

    2) How many devices can be connected to the FSMC. According to th
    Reference Manual at section 31.4 on page 1219 there ist support for 4
    SRAM, 2 x NAND Flash, 1 x PC Card. But if you take a look at pi
    configuration there are only 5 pins which can be used as slave select i
    alternate FSMC function. Do I have this right? Only up to 5 devices can b
    controlled by the FSMC simultaneously?

    3) I would like to interface a Compact Flash by means of the FSM
    peripheral and DMA Controller. Is it possible in that configuration t
    write a sector of data (512 Bytes) to the CF-Cardw controlled by the DMA
    In that case is there furthermore the chance to access external ram or th
    sja1000 if a DMA transaction is progressing in background or do I have t
    wait until the whole DMA transaction succeeds? What if I initiate anothe
    DMA transaction form internal SRAM to external SRAM with higher priorit
    than the Compact Flash DMA transaction. Does the STM32 handle thes
    transactions consecutively or effectivly parallel?

    SJA1000 Datasheet: http://www.nxp.com/documents/data_sheet/SJA1000.pdf
    STM32 Reference Manual
    http://www.st.com/internet/com/TECH...AL_LITERATURE/REFERENCE_MANUAL/CD00225773.pdf

    Thanks a lot!!
     
    christoph531, Feb 14, 2012
    #1
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