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SPI slave select signals

Discussion in 'Embedded' started by praveen.kantharajapura, May 30, 2005.

  1. Hi all,

    In an SPI interface i have got 4 slaves and one master
    What i wanted to know is wether the master can assert two slave
    selects(SS_N) simultaneously OR is there a restriction that master can
    assert only one slave select.

    Does SPI standard dictate anything!!!

    Any comments on this would be appreciated.

    praveen.kantharajapura, May 30, 2005
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  2. praveen.kantharajapura

    larwe Guest

    In an SPI interface i have got 4 slaves and one master
    The slave will drive its MISO pin while selected.
    larwe, May 30, 2005
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  3. praveen.kantharajapura

    GMM50 Guest

    Depends on the design of the master. The NIOS II used in the Altera
    FPGA permits me to asers any number of the SPI select lines.

    But also as has been pointed out if the slaves all try to respond with
    data you've got problems on the SOMI singal line.

    GMM50, May 30, 2005
  4. praveen.kantharajapura

    Al Clark Guest

    wrote in @f14g2000cwb.googlegroups.com:
    The SPI can certainly assert multiple slave selects. The restriction is on
    the slaves. No more than one slave can drive the MISO line at the same

    There are many SPI slave devices that are write only (No MISO connection).


    1. Configuring multiple data converters with the same instructions. You
    might reset the parts with the same instruction and address the parts
    independently for gain settings.
    Al Clark, May 30, 2005
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