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uC or standalone SPI slave with 25 MHz ? (Receiver only would be enough)

Discussion in 'Embedded' started by Martin Maurer, Mar 23, 2006.

  1. Hello,

    is there any uC or standalone controller which can receive SPI data with 25
    MBit/s ? I need this for a SDIO tracer (acting like a SPI slave), which is
    sending 6 bytes each time. I saw different implementation for SPI in an
    FPGA, is there one which is working / preferable ? A small FIFO for the 48
    bit packets would be nice. I know there are tracers which can be bought, but
    for a hobby project they are too expensive...

    Regards,

    Martin
     
    Martin Maurer, Mar 23, 2006
    #1
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  2. Sorry, wrong interface: Replace SPI by SD mode (1 bit / 4 bit interface) !

    Regards,

    Martn
     
    Martin Maurer, Mar 23, 2006
    #2
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  3. Martin,

    if the SPI mode is still an option, the LPC2103 would do a great job
    using the SSP option including your buffer you wanted. 4-bit parallel
    would be slower though because that device does not have the dedicated
    SD interface.

    An Schwob
     
    An Schwob in the USA, Mar 23, 2006
    #3
  4. Sounds like a CPLD problem, something like the MachXO from lattice ?

    -jg
     
    Jim Granville, Mar 24, 2006
    #4
  5. Hello,

    first many thanks for your answer !
    According to the UserManual of LPC2103 (prel. 2. dec. 2005), on page 177f is
    the description of the

    SSP Clock Prescale Register (SSPCPSR - 0xE006 8010).
    Important: the SSPCPSR value must be properly initialized or the SSP
    controller will not
    be able to transmit data correctly. In case of an SSP operating in the
    master mode, the
    CPSDVSRmin = 2, while in case of the slave mode CPSDVSRmin = 12.

    So the maximum frequency in slave mode seems to be 70 MHz / 12 = 5,8 MHz.
    This is unfortunately far away from my requirement...
    The older ones like the LPC2148, can only be used with 60 MHz.

    Regards,

    Martin
     
    Martin Maurer, Mar 24, 2006
    #5
  6. Martin Maurer

    Antti Guest

    1 any CPLD would do
    2 its better to use small FPGA that support on chip logic analyzer :)

    I have made a small break outboard from SD card to GOP module pictures
    here

    http://xilant.com/content/view/33/55/

    but you can use any other FPGA

    Antti

    hm i have some problems implementing MMC memory card slave, my FPGA is
    recognized as media by WinXP, but when i try to write it says write
    protected :(, well I am not doing any tracing, so it may be that I also
    need to implement the SD protocol tracer
     
    Antti, Mar 24, 2006
    #6
  7. I'd suggest getting a cheap Xilinx Spartan-3 eval board. S3 has plenty of RAM on board, and it's
    dual-port, so VERY easy to use for acquisition buffers etc. for this type of thing, as the read and
    write processes have their own individual ports and clocks.
    Also this task is sufficiently simple that it will use a tiny proportion of the chip, and you don't
    need to worry about timing as the chip is 10x faster than you need.
    These 2 factors mean you don't need to spend time doing simulation etc., as the compile
    -debug-recompile time is fast (~30 secs) , and you don't need to worry about timing analysis as it
    will be fast enough with time to spare.
     
    Mike Harrison, Mar 24, 2006
    #7
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