1. This forum section is a read-only archive which contains old newsgroup posts. If you wish to post a query, please do so in one of our main forum sections (here). This way you will get a faster, better response from the members on Motherboard Point.

Unaligned memory access through pointer in cortex-m3

Discussion in 'Embedded' started by kishor, Sep 18, 2011.

  1. kishor

    kishor Guest

    Hi friends,
    I am using stellaris LM3s6965 micro-controller, Keil (MDK-ARM 4.20) as
    IDE.

    I want to know the alignment restrictions on using pointer of
    following type.

    Uint8_t * (unsigned char 8-bit)
    Uint16_t * (unsigned 16-bit)
    Uint32_t * (unsigned 32-bit)

    I need to access 32-bit or 16-bit data from a memory buffer. There is
    no guarantee that address will be aligned. In this case what should I
    do?


    Thanks & regards,
    Kishore.
     
    kishor, Sep 18, 2011
    #1
    1. Advertisements

  2. kishor

    Arlet Ottens Guest

    I'm not familiar with the LM3s6965, but the Cortex-M3 core allows
    unaligned accesses. It does have the option to generate a fault on such
    an access, so you have to make sure this is disabled (this is the
    default after a reset)

    For best performance, you'd want to use aligned accesses as much as
    possible, though.
     
    Arlet Ottens, Sep 18, 2011
    #2
    1. Advertisements

  3. kishor

    linnix Guest

    Declare the buffers as 32 bits array. The compiler should take care
    of the alignment.
     
    linnix, Sep 18, 2011
    #3
  4. Why "there is no guarantee"? Do you have control on how these buffers
    are defined/created?

    If they are "malloced", they should be aligned properly for all
    built-in data types.

    If they are defined explicitly, tricks like this will assure proper
    alignment:

    union align32
    {
    Uint32_t anchor;
    Uint8_t buffer8[???];
    Uint16_t buffer16[???];
    };

    Your compiler may provide something like "#pragma align" to do the
    same, (I'm not familiar with Keil tools), or a #pragma to control what
    memory section is used for the buffers, and then the alignment for
    that section can be specified in the linker configuration file.

    If none of the above is doable, you can just take a performance hit
    when accessing unaligned 16/32-bit data.

    Lastly, if you need the code to be portable to architectures that will
    not allow unaligned memory accesses, write read_u16(...) /
    write_u16(...) / read_u32(...) / write_u32(...) functions working on
    8-bit values only.
     
    Roberto Waltman, Sep 19, 2011
    #4
  5. kishor

    kishor Guest

    Thanks for quick replies.
    The buffer is 8-bit array of 512 bytes. It contains data protocol
    mixed with 8-bit & 16-bit data types.
    so all data access can not be aligned.

    Method -1
    Disable the unaligned access fault
    Read unaligned data from buffer
    Enable the unaligned access fault

    Did disable/enable "unaligned access fault" process takes time?

    Method - 2
    Read multiple 8-bit data through 8-bit pointer
    Pack them to 16-bit or 32-bit variable

    Which is the better option for efficiency & performance.
    I don't want to port this code outside of cortex-m3.

    Thanks & regards,
    Kishore.
     
    kishor, Sep 19, 2011
    #5
  6. kishor

    kishor Guest

    Thanks for quick replies.
    The buffer is 8-bit array of 512 bytes. It contains data protocol
    mixed with 8-bit & 16-bit data types.
    so all data access can not be aligned.

    Method -1
    Disable the unaligned access fault
    Read unaligned data from buffer
    Enable the unaligned access fault

    Did disable/enable "unaligned access fault" process takes time?

    After disabling the unaligned memory access fault, will its
    performance affects on aligned memory access too?
    If not then I can disable the fault at reset. I will try aligned
    memory access as much as possible.

    Method - 2
    Read multiple 8-bit data through 8-bit pointer
    Pack them to 16-bit or 32-bit variable

    Which is the better option for efficiency & performance.
    I don't want to port this code outside of cortex-m3.

    Thanks & regards,
    Kishore.
     
    kishor, Sep 19, 2011
    #6
  7. kishor

    Arlet Ottens Guest

    The buffer is 8-bit array of 512 bytes. It contains data protocol
    Enabling/disabling the fault only takes a single write to a register, so
    it's negligible. You could also leave it disabled all the time, as long
    as you pay attention to the alignment of your other variables.
    Unaligned reads are going to be faster than single byte reads and
    assembling the data yourself.

    In some cases there are some other options, such as copying a block of
    data to align all its variables at the same time. Of course, this only
    works if all variables inside the block are mis-aligned in the same way.
    This may be combined with CRC calculations and/or copying the headers to
    faster memory.
     
    Arlet Ottens, Sep 19, 2011
    #7
  8. kishor

    kishor Guest

    Thanks Arlet Ottens.
     
    kishor, Sep 19, 2011
    #8
    1. Advertisements

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.