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Using opencores I2S as master

Discussion in 'Embedded' started by cbr, Oct 19, 2006.

  1. cbr

    cbr Guest

    Sorry for the cross postings but I really need help.

    I'm trying to use the Opencores I2S master logic as the driver for my
    test platform to generate test audio signals.

    The core came configured with SCK = 2.77 MHz and WS(left/right clock)=
    69.44 KHz.

    I would like to be able to reconfigure the core to generate SCK=3.07MHz

    and WS=48 KHz.

    I played around with the conf variable but could not get the ratio I'm
    looking for.

    I read the documentation but I still cannot understand. An explanation
    would certainly help.

    According to the manual,
    The sample rate is given by bit_rate/(RES * 2)

    If I choose the sample rate to be 48 KHz, and the resolution is
    the bit rate would be 1.92 Mbps.

    However, the RATIO would then be calculated as follows.

    RATIO= (wishbone_bus_clock - (sample_rate * RES * 8)) /
    (sample_rate * RES * 4)

    wishbone_bus_clock= 50 MHz
    sample rate = 48 KHz
    RES=20 bits

    which would then be equal to ~22 (10110)
    This is not giving me the values of 48KHz for WS and 3.072 MHz for

    Could you please help?

    cbr, Oct 19, 2006
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