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What does PC1066 mean, and and what advantage does a 1:1 ratio confer?

Discussion in 'Overclocking' started by Phil Weldon, Apr 23, 2007.

  1. Phil Weldon

    Phil Weldon Guest

    What does PC1066 mean, and and what advantage does a 1:1 ratio confer?

    I consider the question definitively setteled. The CPU clock : memory clock
    ratio is identical to the FSB : memory bus ratio. The nomenclature is
    murky, but DDR2 PC1066 memory is qualified to run with a memory bus of 1066
    MHz. The CPU clock : memory clock ratio as it appears on nVidia 680i SLI
    motherboards represents the FSB : memory bus ratio. DDR2 PC1066 memory is
    required to operate at a 1:1 FSB: memory bus ratio (unless lower rated
    memory is overclocked.)

    For this system
    E4300/ EVGA 680i / Patriot SLI-Ready DDR2 PC1066
    FSB at 1200 MHz for CPU speed of 2.7 GHz

    Three memory benchmarks in SiSoft Sandra 2007 ver 2007.4.11.22
    (Memory Latency, Cache and Memory, Memory Bandwidth)
    with memory timing held constant for all memory bus speeds

    (Memory timing settings in EVGA 680i BIOS)
    SLI Memory [Disabled]
    tCL: 5
    tRCD: 5
    tRP: 5
    tRAS: 16
    CMD: 2T
    tRRD: 3
    tRC: 21
    tWR: 9
    tREF: 7.8 ns

    Gave the following results with memory bus speeds of 400 MHz, 600 MHz, 800
    MHz, 1200 MHz -
    __________
    Memory bus = 400 MHz

    **Memory Latency**
    Random 16 MByte 126.6 ns / 341.7 clocks
    Linear 16 MByte 15.4 ns / 41.6 clocks

    **Cache and Memory**
    Combined Index 12548
    Speed factor 104.6

    **Memory Bandwidth**
    Int. Buffered 4401
    Float Buffered 4368
    Est. Efficiency 46%
    ____________
    Memory bus = 600 MHz

    **Memory Latency**
    Random 16 MByte 91.8 ns / 247.8 clocks
    Linear 16 MBytes 11.7 ns / 31.6 clocks

    **Cache and Memory**
    Combined Index 15075
    Speed factor 68.7

    **Memory Bandwidth**
    Int. Buffered 5567
    Float Buffered 5091
    Est. Efficiency 58%
    __________
    Memory bus = 800 MHz

    **Memory Latency**
    Random 16 MByte 81.9 ns / 221.2 clocks
    Linear 16 MByte 11.1 ns / 29.9 clocks

    **Cache and Memory**
    Combined Index 166384
    Speed factor 53.4

    **Memory Bandwidth**
    Int. Buffered 6042
    Float Buffered 6021
    Est. Efficiency 63%
    __________
    Memory bus = 1200 MHz

    **Memory Latency**
    Random 16 MByte 63.5 ns / 171.3 clocks
    Linear 16 MByte 9.3 ns / 25.4 clocks

    **Cache and Memory**
    Combined Index 19725
    Speed Factor 36.9

    **Memory Bandwidth**
    Int. Buffered: 6438
    Float Buffered 6442
    Est. Efficiency 67%
    __________

    Hope this helps.

    Phil Weldon
     
    Phil Weldon, Apr 23, 2007
    #1
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  2. Phil Weldon

    Paul Guest

    The processor FSB is 64 bits wide. If operating at FSB1066, data transfer
    rate is a maximum of 1066 * 8 bytes = 8528MB/sec.

    In a dual channel setup, you have DDR2-1066 (PC2-8500) on each channel.
    As the number implies, that means each channel transfers at 8500MB/sec,
    and two channels transfer at 17000MB/sec. That is twice the rate that
    the FSB can handle.

    So, what of it ? The Intel architecture features an external memory
    controller. The memory controller is located on the Northbridge
    chip. In addition to the connection of the processor FSB and the
    memory channels, there are also the PCI Express lanes for the video
    card. This could be, for example, PCI Express x16, at 4000MB/sec
    transmit and 4000MB/sec receive. So you could have the processor doing
    a burst, and the video card doing a bidirectional burst (if such a
    thing is possible), and that would more or less fill the memory bus.
    The Northbridge also has the DMI interface (hub bus), which could be
    another 4 PCI Express x1 lanes worth.

    So, in all of that, is there something magic about the clocks on
    the memory and FSB ?

    Actually, due to the strap in the Northbridge, there is a bit of
    unpredictability, about what will happen to performance as you
    overclock. In fact, there is a difference in overclock results,
    between "nominal BIOS/clockgen overclock" versus "overclock via BIOS".
    And that is due to how the Northbridge strap is set up by the BIOS.
    Since I like to back up these enthusiast concepts, with a trip to
    the datasheet, I was disappointed to find no mention of any of the
    details of any "Strap" in the Intel docs. Nor of any "latency setting"
    in the Northbridge, that apparently the BIOS sets up. But people
    did do enough testing and presentation of their results, to show
    there is an appreciable difference between the two overclock methods,
    which lends credibility to the strap concept. Even if the proponent of
    the strap theory is not able to explain it very well (i.e. in a way
    that a hardware designer would understand).

    So there are days of reading material ahead of you, if you wish
    to learn the details of Core2 overclocking. You have to slog
    through a lot of enthusiast chatter, to get nuggets of information.

    In case you missed the point of the above two paragraphs, it is
    this. You should *benchmark* your overclocking setup, and not
    stare at the clocks. The memory and core clock on a Core2 Duo setup,
    don't tell the whole story. In fact, you may find a counterintuitive
    result, where a setup with a lower set of clock values, is giving
    a higher benchmark like SuperPI. Thus, on Core2 Duo, you don't stop
    and crack open a beer, after just cranking the clock. There is more
    to it than that. And kudos to the guys who took the time to test
    and figure it out. I doubt I would have bothered.

    Anandtech did some testing here, and in these results, the biggest
    "jump" might be at DDR2-533. I believe the top five results are
    with a constant core clock, while the bottom three are different.

    http://www.anandtech.com/memory/showdoc.aspx?i=2732&p=4

    I would say, rather than "the question definitively setteled", you
    are now on a "journey of discovery".

    Very little of this is explained in datasheets, which annoys me
    greatly. I expected better of Intel. I'm not even sure there
    is a nice tutorial anywhere, that sums up all the results
    collected so far.

    Paul
     
    Paul, Apr 24, 2007
    #2
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  3. Phil Weldon

    Phil Weldon Guest

    | The processor FSB is 64 bits wide. If operating at FSB1066, data transfer
    | rate is a maximum of 1066 * 8 bytes = 8528MB/sec.
    |
    | In a dual channel setup, you have DDR2-1066 (PC2-8500) on each channel.
    | As the number implies, that means each channel transfers at 8500MB/sec,
    | and two channels transfer at 17000MB/sec. That is twice the rate that
    | the FSB can handle.
    |
    | So, what of it ?
    ..
    ..
    | So, in all of that, is there something magic about the clocks on
    | the memory and FSB ?

    All of what? You deleted almost the entire original post.
    | So there are days of reading material ahead of you, if you wish
    | to learn the details of Core2 overclocking. You have to slog
    | through a lot of enthusiast chatter, to get nuggets of information.
    ..
    ..
    I too am annoyed by the murky nomenclature. My post is part of an ongoing
    discussion in this newsgroup about the utility of DDR2 memory with ratings
    above PC533. The numbers I posted are an aid to understanding that using a
    1:1 FSB : memory bus ratio when the FSB speed is 1066 MHz requires DDR2
    memory that will operate at PC1066 levels. Nothing more.

    You are welcome to YOUR voyage of discovery, but I see it as a quest
    separate from the FSB : memory bus ratio. It also does not aid a discussion
    to delete almost the entire original post when you reply.

    Phil Weldon


    | Phil Weldon wrote:
    | > What does PC1066 mean, and and what advantage does a 1:1 ratio confer?
    | >
    | > I consider the question definitively setteled.
    |
    | The processor FSB is 64 bits wide. If operating at FSB1066, data transfer
    | rate is a maximum of 1066 * 8 bytes = 8528MB/sec.
    |
    | In a dual channel setup, you have DDR2-1066 (PC2-8500) on each channel.
    | As the number implies, that means each channel transfers at 8500MB/sec,
    | and two channels transfer at 17000MB/sec. That is twice the rate that
    | the FSB can handle.
    |
    | So, what of it ? The Intel architecture features an external memory
    | controller. The memory controller is located on the Northbridge
    | chip. In addition to the connection of the processor FSB and the
    | memory channels, there are also the PCI Express lanes for the video
    | card. This could be, for example, PCI Express x16, at 4000MB/sec
    | transmit and 4000MB/sec receive. So you could have the processor doing
    | a burst, and the video card doing a bidirectional burst (if such a
    | thing is possible), and that would more or less fill the memory bus.
    | The Northbridge also has the DMI interface (hub bus), which could be
    | another 4 PCI Express x1 lanes worth.
    |
    | So, in all of that, is there something magic about the clocks on
    | the memory and FSB ?
    |
    | Actually, due to the strap in the Northbridge, there is a bit of
    | unpredictability, about what will happen to performance as you
    | overclock. In fact, there is a difference in overclock results,
    | between "nominal BIOS/clockgen overclock" versus "overclock via BIOS".
    | And that is due to how the Northbridge strap is set up by the BIOS.
    | Since I like to back up these enthusiast concepts, with a trip to
    | the datasheet, I was disappointed to find no mention of any of the
    | details of any "Strap" in the Intel docs. Nor of any "latency setting"
    | in the Northbridge, that apparently the BIOS sets up. But people
    | did do enough testing and presentation of their results, to show
    | there is an appreciable difference between the two overclock methods,
    | which lends credibility to the strap concept. Even if the proponent of
    | the strap theory is not able to explain it very well (i.e. in a way
    | that a hardware designer would understand).
    |
    | So there are days of reading material ahead of you, if you wish
    | to learn the details of Core2 overclocking. You have to slog
    | through a lot of enthusiast chatter, to get nuggets of information.
    |
    | In case you missed the point of the above two paragraphs, it is
    | this. You should *benchmark* your overclocking setup, and not
    | stare at the clocks. The memory and core clock on a Core2 Duo setup,
    | don't tell the whole story. In fact, you may find a counterintuitive
    | result, where a setup with a lower set of clock values, is giving
    | a higher benchmark like SuperPI. Thus, on Core2 Duo, you don't stop
    | and crack open a beer, after just cranking the clock. There is more
    | to it than that. And kudos to the guys who took the time to test
    | and figure it out. I doubt I would have bothered.
    |
    | Anandtech did some testing here, and in these results, the biggest
    | "jump" might be at DDR2-533. I believe the top five results are
    | with a constant core clock, while the bottom three are different.
    |
    | http://www.anandtech.com/memory/showdoc.aspx?i=2732&p=4
    |
    | I would say, rather than "the question definitively setteled", you
    | are now on a "journey of discovery".
    |
    | Very little of this is explained in datasheets, which annoys me
    | greatly. I expected better of Intel. I'm not even sure there
    | is a nice tutorial anywhere, that sums up all the results
    | collected so far.
    |
    | Paul
     
    Phil Weldon, Apr 24, 2007
    #3
  4. Phil, the case is so well settled that here are my results:

    E6600 / P5W DH / Corsair Value Select DDR2 667 (the cheapest Corsair DDR2
    667 there is)
    FSB at 1333 (4 x 333 MHz) for CPU speed of 3.0 MHz
    Memory latency timings: 4-4-4-12-16 (tCAS-tRC-tRP-tRAS-tRC)

    Memory bus = 333 MHz / CPU-Z reporting 1:1 ratio

    **Memory Latency**
    Random 16 MByte 64.1 ns / 192.4 clocks
    Linear 16 MByte 11.0 ns / 33.0 clocks

    **Cache and Memory**
    Combined Index 23812
    Speed factor 40.3

    **Memory Bandwidth**
    Int. Buffered 6630
    Float Buffered 6327
    Est. Efficiency 60%

    Which are close to your results at Memory bus = 1200 MHz.
    Now what? Don't tell me that I overclock my mem by a factor of 2, I don't
    believe it.
    Could you maybe download CPU-Z, launch it and tell what it says under the
    Memory tab? You should also look at the SPD tab.

    Michka

     
    Michel R. Carleer, Apr 24, 2007
    #4
  5. I would like to emphasize that using dual channel memory does not mean that
    you increase the mem bandwidth by a factor of 2. Because it does not mean
    that you double the width from 64 bits to 128. It means that you read one
    piece of data (64 bits) from one bank, and the next piece of data from the
    other bank. In order to overcome at least partly the latency problem.

    Michka
     
    Michel R. Carleer, Apr 24, 2007
    #5
  6. Sorry guys, small typo, the Memory Bandwidth Int. Buffered should read 6330,
    not 6630.

    Michka
     
    Michel R. Carleer, Apr 24, 2007
    #6
  7. Phil Weldon

    Paul Guest

    I thought your post had something to do with synchronous transfer, as if there
    was something magic about the 1:1 ratio. The bandwidth ratio is
    2:1 between dual channel memory and the processor, for your stated case
    of DDR2-1066 and FSB1066.

    Clock, strictly speaking, is a physical signal connected to a chip. On the
    processor, the input clock is 266MHz. The FSB is quad pumped. It means there
    are four data phases per clock cycle. As far as I know, there isn't an actual
    clock passed between the processor and northbridge at 1066MHz. So there are
    1066 million transfers per second of 8 bytes per transfer, for 8523MB/sec
    on the FSB. But the clock fed to both the processor and the northbridge, is
    at the lower rate of 266MHz.

    According to the P965 datasheet, the Northbridge puts out a 266, 333, or 400MHz
    clock to each DIMM. (Corresponding to DDR2-533, DDR2-667, and DDR2-800.) If
    we extrapolate to the overclocked condition, that means the memory clock
    is 533MHz when the memory is DDR2-1066.

    So the ratio between memory clock and processor clock is 2:1, and the
    reason for that, is the difference between quad pumped on the FSB
    versus double data rate on the memory interface.

    So, by all means, divide 1066 by 1066. The units in each case are
    "million transfers per second" and not megahertz, as megahertz
    applies to clocks. FSB1066 and DDR2-1066 apply to the data busses
    in their respective cases and their transfer rates.

    1) The clock ratio is 2:1
    2) The bandwidth ratio is 2:1 (assuming dual channel as the norm)
    3) The "bus transfer rate" ratio is 1:1

    I snipped the rest of your post, because I was answering the 1:1
    conclusion for clocks, which is not correct.

    Paul
     
    Paul, Apr 24, 2007
    #7
  8. Phil Weldon

    Phil Weldon Guest

    'Michka' wrote:
    | Phil, the case is so well settled that here are my results:
    |
    | E6600 / P5W DH / Corsair Value Select DDR2 667 (the cheapest Corsair DDR2
    | 667 there is)
    | FSB at 1333 (4 x 333 MHz) for CPU speed of 3.0 MHz
    | Memory latency timings: 4-4-4-12-16 (tCAS-tRC-tRP-tRAS-tRC)
    |
    | Memory bus = 333 MHz / CPU-Z reporting 1:1 ratio
    |
    | **Memory Latency**
    | Random 16 MByte 64.1 ns / 192.4 clocks
    | Linear 16 MByte 11.0 ns / 33.0 clocks
    |
    | **Cache and Memory**
    | Combined Index 23812
    | Speed factor 40.3
    |
    | **Memory Bandwidth**
    | Int. Buffered 6630
    | Float Buffered 6327
    | Est. Efficiency 60%
    |
    | Which are close to your results at Memory bus = 1200 MHz.
    | Now what? Don't tell me that I overclock my mem by a factor of 2, I don't
    | believe it.
    | Could you maybe download CPU-Z, launch it and tell what it says under the
    | Memory tab? You should also look at the SPD tab.
    _____

    Sure; it can not be more tedious than running the multiple tests with SiSoft
    Sandra B^) And could you report the additional memory timings for your
    Corsair DDR2 667 (CMD, tRRD, tWR, and tREF)? I have these memory timing
    parameters set very loose so that they could remain the same over all the
    memory bus settings.

    Thanks for pointing out what 'Dual Channel' means. We will chip away at
    this problem.

    Phil Weldon


    | Phil, the case is so well settled that here are my results:
    |
    | E6600 / P5W DH / Corsair Value Select DDR2 667 (the cheapest Corsair DDR2
    | 667 there is)
    | FSB at 1333 (4 x 333 MHz) for CPU speed of 3.0 MHz
    | Memory latency timings: 4-4-4-12-16 (tCAS-tRC-tRP-tRAS-tRC)
    |
    | Memory bus = 333 MHz / CPU-Z reporting 1:1 ratio
    |
    | **Memory Latency**
    | Random 16 MByte 64.1 ns / 192.4 clocks
    | Linear 16 MByte 11.0 ns / 33.0 clocks
    |
    | **Cache and Memory**
    | Combined Index 23812
    | Speed factor 40.3
    |
    | **Memory Bandwidth**
    | Int. Buffered 6630
    | Float Buffered 6327
    | Est. Efficiency 60%
    |
    | Which are close to your results at Memory bus = 1200 MHz.
    | Now what? Don't tell me that I overclock my mem by a factor of 2, I don't
    | believe it.
    | Could you maybe download CPU-Z, launch it and tell what it says under the
    | Memory tab? You should also look at the SPD tab.
    |
    | Michka
    |
    | | > What does PC1066 mean, and and what advantage does a 1:1 ratio confer?
    | >
    | > I consider the question definitively setteled. The CPU clock : memory
    | > clock
    | > ratio is identical to the FSB : memory bus ratio. The nomenclature is
    | > murky, but DDR2 PC1066 memory is qualified to run with a memory bus of
    | > 1066
    | > MHz. The CPU clock : memory clock ratio as it appears on nVidia 680i
    SLI
    | > motherboards represents the FSB : memory bus ratio. DDR2 PC1066 memory
    is
    | > required to operate at a 1:1 FSB: memory bus ratio (unless lower rated
    | > memory is overclocked.)
    | >
    | > For this system
    | > E4300/ EVGA 680i / Patriot SLI-Ready DDR2 PC1066
    | > FSB at 1200 MHz for CPU speed of 2.7 GHz
    | >
    | > Three memory benchmarks in SiSoft Sandra 2007 ver 2007.4.11.22
    | > (Memory Latency, Cache and Memory, Memory Bandwidth)
    | > with memory timing held constant for all memory bus speeds
    | >
    | > (Memory timing settings in EVGA 680i BIOS)
    | > SLI Memory [Disabled]
    | > tCL: 5
    | > tRCD: 5
    | > tRP: 5
    | > tRAS: 16
    | > CMD: 2T
    | > tRRD: 3
    | > tRC: 21
    | > tWR: 9
    | > tREF: 7.8 ns
    | >
    | > Gave the following results with memory bus speeds of 400 MHz, 600 MHz,
    800
    | > MHz, 1200 MHz -
    | > __________
    | > Memory bus = 400 MHz
    | >
    | > **Memory Latency**
    | > Random 16 MByte 126.6 ns / 341.7 clocks
    | > Linear 16 MByte 15.4 ns / 41.6 clocks
    | >
    | > **Cache and Memory**
    | > Combined Index 12548
    | > Speed factor 104.6
    | >
    | > **Memory Bandwidth**
    | > Int. Buffered 4401
    | > Float Buffered 4368
    | > Est. Efficiency 46%
    | > ____________
    | > Memory bus = 600 MHz
    | >
    | > **Memory Latency**
    | > Random 16 MByte 91.8 ns / 247.8 clocks
    | > Linear 16 MBytes 11.7 ns / 31.6 clocks
    | >
    | > **Cache and Memory**
    | > Combined Index 15075
    | > Speed factor 68.7
    | >
    | > **Memory Bandwidth**
    | > Int. Buffered 5567
    | > Float Buffered 5091
    | > Est. Efficiency 58%
    | > __________
    | > Memory bus = 800 MHz
    | >
    | > **Memory Latency**
    | > Random 16 MByte 81.9 ns / 221.2 clocks
    | > Linear 16 MByte 11.1 ns / 29.9 clocks
    | >
    | > **Cache and Memory**
    | > Combined Index 166384
    | > Speed factor 53.4
    | >
    | > **Memory Bandwidth**
    | > Int. Buffered 6042
    | > Float Buffered 6021
    | > Est. Efficiency 63%
    | > __________
    | > Memory bus = 1200 MHz
    | >
    | > **Memory Latency**
    | > Random 16 MByte 63.5 ns / 171.3 clocks
    | > Linear 16 MByte 9.3 ns / 25.4 clocks
    | >
    | > **Cache and Memory**
    | > Combined Index 19725
    | > Speed Factor 36.9
    | >
    | > **Memory Bandwidth**
    | > Int. Buffered: 6438
    | > Float Buffered 6442
    | > Est. Efficiency 67%
    | > __________
    | >
    | > Hope this helps.
    | >
    | > Phil Weldon
    | >
    | >
    |
    |
     
    Phil Weldon, Apr 24, 2007
    #8
  9. Phil Weldon

    Thomas Guest

    <Another very big snip>

    What does SLI memory mean? It's not eVGA's way of saying 'dual channel' ?
    :)

    Sorry if this is a stupid question. I hope to join this discussion with some
    numbers of myself soon. I've started to threathen my supplier :p
     
    Thomas, Apr 24, 2007
    #9
  10. Phil Weldon

    Phil Weldon Guest

    'Michka' wrote:
    | Phil, the case is so well settled that here are my results:
    |
    | E6600 / P5W DH / Corsair Value Select DDR2 667 (the cheapest Corsair DDR2
    | 667 there is)
    | FSB at 1333 (4 x 333 MHz) for CPU speed of 3.0 MHz
    | Memory latency timings: 4-4-4-12-16 (tCAS-tRC-tRP-tRAS-tRC)
    |
    | Memory bus = 333 MHz / CPU-Z reporting 1:1 ratio
    |
    | **Memory Latency**
    | Random 16 MByte 64.1 ns / 192.4 clocks
    | Linear 16 MByte 11.0 ns / 33.0 clocks
    |
    | **Cache and Memory**
    | Combined Index 23812
    | Speed factor 40.3
    |
    | **Memory Bandwidth**
    | Int. Buffered 6630
    | Float Buffered 6327
    | Est. Efficiency 60%
    |
    | Which are close to your results at Memory bus = 1200 MHz.
    | Now what? Don't tell me that I overclock my mem by a factor of 2, I don't
    | believe it.
    | Could you maybe download CPU-Z, launch it and tell what it says under the
    | Memory tab? You should also look at the SPD tab.
    _____

    Evidently PC1066 = DDR2-667;
    I have PC1066 = DDR2-667 memory
    and
    you have PC667 = DDR2-333 memory.

    I have a 1:1 FSB : memory bus ratio and a 1:2 CPU clock : memory clock
    ratio.
    You have a 1:2 FSB : memory bus ratio and a 1:1 CPU clock : memory clock
    ratio.

    **CPU-Z Memory TAB**
    Type: DDR2
    Channels: Dual
    Size: 2048 MBytes

    Timings:
    Frequency - 600 MHz
    FSB: DRAM - 1:2
    CAS# Latency - 5.0 clocks
    RAS# to CAS# Delay - 5 clocks
    RAS# Precharge - 5 clocks
    Cycle Time (Tras) - 5 clocks
    Bank Cycle Time (Trc) - 21 clocks
    Command Rate - 2T

    **CPU-Z SPD TAB**
    Module Size - 1024 MBytes
    Max Bandwidth - PC2-6400 (400 MHz)
    Manufacturer - PDP Systems
    Part Number - PDC21g8500ELK
    EPP - Yes

    Timings Table:
    Frequency 533 MHz
    CAS# Latency - 5.0
    RAS# to CAS# - 5
    RAS# Precharge - 5
    Tras - 9
    Trc - 30
    Command Rate - 27


    The BIOS settings for memory speed for DDR2 nVidia 680i motherboards are
    based on memory bus speeds.

    The BIOS settings for memory speed for DDR2 Intel chipset motherboards are
    based on memory clock speeds.

    I will now attempt to get a 1333 MHz FSB / memory bus of 667 MHz set of
    readings using your memory timings. Also, could you report your CMD (2T or
    1T)?

    Phil Weldon




    | Phil, the case is so well settled that here are my results:
    |
    | E6600 / P5W DH / Corsair Value Select DDR2 667 (the cheapest Corsair DDR2
    | 667 there is)
    | FSB at 1333 (4 x 333 MHz) for CPU speed of 3.0 MHz
    | Memory latency timings: 4-4-4-12-16 (tCAS-tRC-tRP-tRAS-tRC)
    |
    | Memory bus = 333 MHz / CPU-Z reporting 1:1 ratio
    |
    | **Memory Latency**
    | Random 16 MByte 64.1 ns / 192.4 clocks
    | Linear 16 MByte 11.0 ns / 33.0 clocks
    |
    | **Cache and Memory**
    | Combined Index 23812
    | Speed factor 40.3
    |
    | **Memory Bandwidth**
    | Int. Buffered 6630
    | Float Buffered 6327
    | Est. Efficiency 60%
    |
    | Which are close to your results at Memory bus = 1200 MHz.
    | Now what? Don't tell me that I overclock my mem by a factor of 2, I don't
    | believe it.
    | Could you maybe download CPU-Z, launch it and tell what it says under the
    | Memory tab? You should also look at the SPD tab.
    |
    | Michka
    |
    | | > What does PC1066 mean, and and what advantage does a 1:1 ratio confer?
    | >
    | > I consider the question definitively setteled. The CPU clock : memory
    | > clock
    | > ratio is identical to the FSB : memory bus ratio. The nomenclature is
    | > murky, but DDR2 PC1066 memory is qualified to run with a memory bus of
    | > 1066
    | > MHz. The CPU clock : memory clock ratio as it appears on nVidia 680i
    SLI
    | > motherboards represents the FSB : memory bus ratio. DDR2 PC1066 memory
    is
    | > required to operate at a 1:1 FSB: memory bus ratio (unless lower rated
    | > memory is overclocked.)
    | >
    | > For this system
    | > E4300/ EVGA 680i / Patriot SLI-Ready DDR2 PC1066
    | > FSB at 1200 MHz for CPU speed of 2.7 GHz
    | >
    | > Three memory benchmarks in SiSoft Sandra 2007 ver 2007.4.11.22
    | > (Memory Latency, Cache and Memory, Memory Bandwidth)
    | > with memory timing held constant for all memory bus speeds
    | >
    | > (Memory timing settings in EVGA 680i BIOS)
    | > SLI Memory [Disabled]
    | > tCL: 5
    | > tRCD: 5
    | > tRP: 5
    | > tRAS: 16
    | > CMD: 2T
    | > tRRD: 3
    | > tRC: 21
    | > tWR: 9
    | > tREF: 7.8 ns
    | >
    | > Gave the following results with memory bus speeds of 400 MHz, 600 MHz,
    800
    | > MHz, 1200 MHz -
    | > __________
    | > Memory bus = 400 MHz
    | >
    | > **Memory Latency**
    | > Random 16 MByte 126.6 ns / 341.7 clocks
    | > Linear 16 MByte 15.4 ns / 41.6 clocks
    | >
    | > **Cache and Memory**
    | > Combined Index 12548
    | > Speed factor 104.6
    | >
    | > **Memory Bandwidth**
    | > Int. Buffered 4401
    | > Float Buffered 4368
    | > Est. Efficiency 46%
    | > ____________
    | > Memory bus = 600 MHz
    | >
    | > **Memory Latency**
    | > Random 16 MByte 91.8 ns / 247.8 clocks
    | > Linear 16 MBytes 11.7 ns / 31.6 clocks
    | >
    | > **Cache and Memory**
    | > Combined Index 15075
    | > Speed factor 68.7
    | >
    | > **Memory Bandwidth**
    | > Int. Buffered 5567
    | > Float Buffered 5091
    | > Est. Efficiency 58%
    | > __________
    | > Memory bus = 800 MHz
    | >
    | > **Memory Latency**
    | > Random 16 MByte 81.9 ns / 221.2 clocks
    | > Linear 16 MByte 11.1 ns / 29.9 clocks
    | >
    | > **Cache and Memory**
    | > Combined Index 166384
    | > Speed factor 53.4
    | >
    | > **Memory Bandwidth**
    | > Int. Buffered 6042
    | > Float Buffered 6021
    | > Est. Efficiency 63%
    | > __________
    | > Memory bus = 1200 MHz
    | >
    | > **Memory Latency**
    | > Random 16 MByte 63.5 ns / 171.3 clocks
    | > Linear 16 MByte 9.3 ns / 25.4 clocks
    | >
    | > **Cache and Memory**
    | > Combined Index 19725
    | > Speed Factor 36.9
    | >
    | > **Memory Bandwidth**
    | > Int. Buffered: 6438
    | > Float Buffered 6442
    | > Est. Efficiency 67%
    | > __________
    | >
    | > Hope this helps.
    | >
    | > Phil Weldon
    | >
    | >
    |
    |
     
    Phil Weldon, Apr 24, 2007
    #10
  11. SLI is the way nVidia make two video cards work in parallel. I don't know
    however why the main memory should be SLI ready????
    Because I don't know how SLI works. I guess it has to do with how the master
    and slave video cards share the video data.

    Michka

     
    M. R. Carleer, Apr 24, 2007
    #11
  12. Phil,
    My tCMD is 4. With the BIOS of the P5W DH, I don't have access to the
    additional timings you mention. Those are taken directly from the SPD. I
    have no control on them, nor can I see their value in the BIOS.
    I am using DDR2 667 (PC2-5300) mem modules. I/O bus clock = 333 MHz (the
    same as the FSB clock, hence the 1:1 ratio per CPU-Z definition) and
    internal mem clock = 166 MHz.
    One thing we did not discuss: there is no direct link between the CPU and
    the mem. The CPU and the mem communicate through the northbridge.
    Anyway, there seems to be various definitions of the ratio and the way mem
    modules are named.
    If using your definition (the one you use, that is), my mem modules would be
    PC1333, not PC1066. It is made of DDR2 667 chips.
    The chips are 8 bits wide, and my definition of PC-something (once again,
    the one I use) is PC2-5300 because the mem bus is 64 bits wide.

    Michka

     
    M. R. Carleer, Apr 24, 2007
    #12
  13. Phil Weldon

    Phil Weldon Guest

    'Thomas' wrote, in part:
    | What does SLI memory mean? It's not eVGA's way of saying 'dual channel' ?
    | :)
    _____

    SLI-ready memory is used by nVidia and cooperating DDR2 memory module
    manufacturers for memory speeds that are not yet official and that have
    extended SPD fields that contain timing and voltage information for BIOS use
    in setting higher clock rates and memory bus speeds. In my nVidia 680i
    motherboard BIOS, by selecting 'SLI Ready' [Enabled], when an FSB of 1066
    MHz is selected an FSB : memory bus ratio of 1:1 (CPU clock : memory clock
    ratio of 1:2) is set. The memory timing parameters are automatically
    relaxed to 5-5-5-16 CMD = 2T and the memory voltage is boosted to 2.3 VDC.
    By selecting 'SLI Ready [Disabled] and 'Memory Mode' [Expert] in the BIOS
    the following memory timing parameters can be set manually
    tCL
    tRCD
    tRP
    tRAS
    CMD
    tRRD
    tRC
    tWR
    tREF

    I think this ties into the SLI concept by providing greater bandwidth on the
    memory bus to be shared by PCI-E display adapters and the CPU.

    Phil Weldon

    | Phil Weldon wrote:
    | > What does PC1066 mean, and and what advantage does a 1:1 ratio confer?
    |
    | <VERY BIG SNIP>
    |
    | > (Memory timing settings in EVGA 680i BIOS)
    | > SLI Memory [Disabled]
    |
    | <Another very big snip>
    |
    | What does SLI memory mean? It's not eVGA's way of saying 'dual channel' ?
    | :)
    |
    | Sorry if this is a stupid question. I hope to join this discussion with
    some
    | numbers of myself soon. I've started to threathen my supplier :p
    |
    | --
    | Met vriendelijke groeten, Thomas vd Horst.
    |
    |
     
    Phil Weldon, Apr 24, 2007
    #13
  14. Phil Weldon

    Ed Medlin Guest

    It has to do with the way the memory modules work together as far as I
    know.........Which seems to be
    getting more and more confused daily....:). I never heard the term until
    the later Nvidia based MBs.
    You do not need SLI ready memory to run video cards in SLI, so I would
    assume that the term can be
    used both for the memory and video. I think we are getting far too much into
    all the different terminologies
    instead of what all this really means. I assume that SLI ready memory is
    akin to "matched" memory in terms
    of dual channel memory. It may just work in a different way. I take no
    offense in being corrected if I am wrong.
    That is how we all learn........:)


    Ed
     
    Ed Medlin, Apr 24, 2007
    #14
  15. Phil Weldon

    Phil Weldon Guest

    'Michka' wrote:
    | My tCMD is 4. With the BIOS of the P5W DH, I don't have access to the
    | additional timings you mention. Those are taken directly from the SPD. I
    | have no control on them, nor can I see their value in the BIOS.
    | I am using DDR2 667 (PC2-5300) mem modules. I/O bus clock = 333 MHz (the
    | same as the FSB clock, hence the 1:1 ratio per CPU-Z definition) and
    | internal mem clock = 166 MHz.
    | One thing we did not discuss: there is no direct link between the CPU and
    | the mem. The CPU and the mem communicate through the northbridge.
    | Anyway, there seems to be various definitions of the ratio and the way mem
    | modules are named.
    | If using your definition (the one you use, that is), my mem modules would
    be
    | PC1333, not PC1066. It is made of DDR2 667 chips.
    | The chips are 8 bits wide, and my definition of PC-something (once again,
    | the one I use) is PC2-5300 because the mem bus is 64 bits wide.
    _____

    Yes, I mistyped. Your memory is XXXX-333/XXXX-667/XXXX-5300 and various
    other designations used variously! The XXXX-333 designation is based on the
    actual memory clock speed, the XXXX-667 is based on the memory bus speed,
    and the PC5300 is based on the theoretical maximum bandwidth.

    Crucial, a division of Micron, now produces SLI-ready memory. (see
    http://www.crucial.com/library/sli_epp.asp
    and
    http://www.crucial.com/store/partspecs.aspx?imodule=BL2KIT12864AA1065 ).

    Perhaps the entry of Micron/Crucial will help bring order to the
    nomenclature wars (Crucial uses the designation PC2-8500 to equal DDRII-1066
    but also states
    "Ballistix 240-pin DIMMs are used to provide DDR2 SDRAM memory for desktop
    computers. DDR2 is a leading-edge generation of memory with an improved
    architecture that allows it to transmit data very fast. Ballistix 240-pin
    DIMMs are available in DDR2 PC2-4200 SDRAM (DDR2 533), DDR2 PC2-5300 SDRAM
    (DDR2 667), DDR2 PC2-6400 (DDR2 800), and DDR2 PC2-8500 (DDR2 1066)."

    so maybe not. Very likely a would-be world leader needs a clear plan and
    widespread support.

    Perhaps the PC6400/PC8500/ ... designations are at the moment the least
    ambiguous. XXXX-6400 identifies DDR2 memory qualified for a memory bus of
    667 MHz and a memory clock of 333 MHz. XXXX-8500 identifies DDR2 memory
    qualified for a memory bus of 1066 MHz and a memory clock of 533 MHz.

    On question; for the benchmark results I posted the CMD was 2T (1T is the
    other choice, usable when the memory is run at lower speeds.) What does
    your tCMD = 4 represent?) I can run a benchmark with an FSB of 1333 MHz, a
    memory bus of 667 MHz, and a memory clock of 333 MHz by setting the E4300
    multiplier to 8 X. I would like to used memory timings as close as possible
    to yours.

    Phil Weldon

    | Phil,
    | My tCMD is 4. With the BIOS of the P5W DH, I don't have access to the
    | additional timings you mention. Those are taken directly from the SPD. I
    | have no control on them, nor can I see their value in the BIOS.
    | I am using DDR2 667 (PC2-5300) mem modules. I/O bus clock = 333 MHz (the
    | same as the FSB clock, hence the 1:1 ratio per CPU-Z definition) and
    | internal mem clock = 166 MHz.
    | One thing we did not discuss: there is no direct link between the CPU and
    | the mem. The CPU and the mem communicate through the northbridge.
    | Anyway, there seems to be various definitions of the ratio and the way mem
    | modules are named.
    | If using your definition (the one you use, that is), my mem modules would
    be
    | PC1333, not PC1066. It is made of DDR2 667 chips.
    | The chips are 8 bits wide, and my definition of PC-something (once again,
    | the one I use) is PC2-5300 because the mem bus is 64 bits wide.
    |
    | Michka
    |
    | | > 'Michka' wrote:
    | > | Phil, the case is so well settled that here are my results:
    | > |
    | > | E6600 / P5W DH / Corsair Value Select DDR2 667 (the cheapest Corsair
    | DDR2
    | > | 667 there is)
    | > | FSB at 1333 (4 x 333 MHz) for CPU speed of 3.0 MHz
    | > | Memory latency timings: 4-4-4-12-16 (tCAS-tRC-tRP-tRAS-tRC)
    | > |
    | > | Memory bus = 333 MHz / CPU-Z reporting 1:1 ratio
    | > |
    | > | **Memory Latency**
    | > | Random 16 MByte 64.1 ns / 192.4 clocks
    | > | Linear 16 MByte 11.0 ns / 33.0 clocks
    | > |
    | > | **Cache and Memory**
    | > | Combined Index 23812
    | > | Speed factor 40.3
    | > |
    | > | **Memory Bandwidth**
    | > | Int. Buffered 6630
    | > | Float Buffered 6327
    | > | Est. Efficiency 60%
    | > |
    | > | Which are close to your results at Memory bus = 1200 MHz.
    | > | Now what? Don't tell me that I overclock my mem by a factor of 2, I
    | don't
    | > | believe it.
    | > | Could you maybe download CPU-Z, launch it and tell what it says under
    | the
    | > | Memory tab? You should also look at the SPD tab.
    | > _____
    | >
    | > Evidently PC1066 = DDR2-667;
    | > I have PC1066 = DDR2-667 memory
    | > and
    | > you have PC667 = DDR2-333 memory.
    | >
    | > I have a 1:1 FSB : memory bus ratio and a 1:2 CPU clock : memory clock
    | > ratio.
    | > You have a 1:2 FSB : memory bus ratio and a 1:1 CPU clock : memory clock
    | > ratio.
    | >
    | > **CPU-Z Memory TAB**
    | > Type: DDR2
    | > Channels: Dual
    | > Size: 2048 MBytes
    | >
    | > Timings:
    | > Frequency - 600 MHz
    | > FSB: DRAM - 1:2
    | > CAS# Latency - 5.0 clocks
    | > RAS# to CAS# Delay - 5 clocks
    | > RAS# Precharge - 5 clocks
    | > Cycle Time (Tras) - 5 clocks
    | > Bank Cycle Time (Trc) - 21 clocks
    | > Command Rate - 2T
    | >
    | > **CPU-Z SPD TAB**
    | > Module Size - 1024 MBytes
    | > Max Bandwidth - PC2-6400 (400 MHz)
    | > Manufacturer - PDP Systems
    | > Part Number - PDC21g8500ELK
    | > EPP - Yes
    | >
    | > Timings Table:
    | > Frequency 533 MHz
    | > CAS# Latency - 5.0
    | > RAS# to CAS# - 5
    | > RAS# Precharge - 5
    | > Tras - 9
    | > Trc - 30
    | > Command Rate - 27
    | >
    | >
    | > The BIOS settings for memory speed for DDR2 nVidia 680i motherboards are
    | > based on memory bus speeds.
    | >
    | > The BIOS settings for memory speed for DDR2 Intel chipset motherboards
    are
    | > based on memory clock speeds.
    | >
    | > I will now attempt to get a 1333 MHz FSB / memory bus of 667 MHz set of
    | > readings using your memory timings. Also, could you report your CMD (2T
    | or
    | > 1T)?
    | >
    | > Phil Weldon
    | >
    | >
    | >
    | >
    | > | > | Phil, the case is so well settled that here are my results:
    | > |
    | > | E6600 / P5W DH / Corsair Value Select DDR2 667 (the cheapest Corsair
    | DDR2
    | > | 667 there is)
    | > | FSB at 1333 (4 x 333 MHz) for CPU speed of 3.0 MHz
    | > | Memory latency timings: 4-4-4-12-16 (tCAS-tRC-tRP-tRAS-tRC)
    | > |
    | > | Memory bus = 333 MHz / CPU-Z reporting 1:1 ratio
    | > |
    | > | **Memory Latency**
    | > | Random 16 MByte 64.1 ns / 192.4 clocks
    | > | Linear 16 MByte 11.0 ns / 33.0 clocks
    | > |
    | > | **Cache and Memory**
    | > | Combined Index 23812
    | > | Speed factor 40.3
    | > |
    | > | **Memory Bandwidth**
    | > | Int. Buffered 6630
    | > | Float Buffered 6327
    | > | Est. Efficiency 60%
    | > |
    | > | Which are close to your results at Memory bus = 1200 MHz.
    | > | Now what? Don't tell me that I overclock my mem by a factor of 2, I
    | don't
    | > | believe it.
    | > | Could you maybe download CPU-Z, launch it and tell what it says under
    | the
    | > | Memory tab? You should also look at the SPD tab.
    | > |
    | > | Michka
    | > |
    | > | | > | > What does PC1066 mean, and and what advantage does a 1:1 ratio
    confer?
    | > | >
    | > | > I consider the question definitively setteled. The CPU clock :
    memory
    | > | > clock
    | > | > ratio is identical to the FSB : memory bus ratio. The nomenclature
    | is
    | > | > murky, but DDR2 PC1066 memory is qualified to run with a memory bus
    of
    | > | > 1066
    | > | > MHz. The CPU clock : memory clock ratio as it appears on nVidia
    680i
    | > SLI
    | > | > motherboards represents the FSB : memory bus ratio. DDR2 PC1066
    | memory
    | > is
    | > | > required to operate at a 1:1 FSB: memory bus ratio (unless lower
    rated
    | > | > memory is overclocked.)
    | > | >
    | > | > For this system
    | > | > E4300/ EVGA 680i / Patriot SLI-Ready DDR2 PC1066
    | > | > FSB at 1200 MHz for CPU speed of 2.7 GHz
    | > | >
    | > | > Three memory benchmarks in SiSoft Sandra 2007 ver 2007.4.11.22
    | > | > (Memory Latency, Cache and Memory, Memory Bandwidth)
    | > | > with memory timing held constant for all memory bus speeds
    | > | >
    | > | > (Memory timing settings in EVGA 680i BIOS)
    | > | > SLI Memory [Disabled]
    | > | > tCL: 5
    | > | > tRCD: 5
    | > | > tRP: 5
    | > | > tRAS: 16
    | > | > CMD: 2T
    | > | > tRRD: 3
    | > | > tRC: 21
    | > | > tWR: 9
    | > | > tREF: 7.8 ns
    | > | >
    | > | > Gave the following results with memory bus speeds of 400 MHz, 600
    MHz,
    | > 800
    | > | > MHz, 1200 MHz -
    | > | > __________
    | > | > Memory bus = 400 MHz
    | > | >
    | > | > **Memory Latency**
    | > | > Random 16 MByte 126.6 ns / 341.7 clocks
    | > | > Linear 16 MByte 15.4 ns / 41.6 clocks
    | > | >
    | > | > **Cache and Memory**
    | > | > Combined Index 12548
    | > | > Speed factor 104.6
    | > | >
    | > | > **Memory Bandwidth**
    | > | > Int. Buffered 4401
    | > | > Float Buffered 4368
    | > | > Est. Efficiency 46%
    | > | > ____________
    | > | > Memory bus = 600 MHz
    | > | >
    | > | > **Memory Latency**
    | > | > Random 16 MByte 91.8 ns / 247.8 clocks
    | > | > Linear 16 MBytes 11.7 ns / 31.6 clocks
    | > | >
    | > | > **Cache and Memory**
    | > | > Combined Index 15075
    | > | > Speed factor 68.7
    | > | >
    | > | > **Memory Bandwidth**
    | > | > Int. Buffered 5567
    | > | > Float Buffered 5091
    | > | > Est. Efficiency 58%
    | > | > __________
    | > | > Memory bus = 800 MHz
    | > | >
    | > | > **Memory Latency**
    | > | > Random 16 MByte 81.9 ns / 221.2 clocks
    | > | > Linear 16 MByte 11.1 ns / 29.9 clocks
    | > | >
    | > | > **Cache and Memory**
    | > | > Combined Index 166384
    | > | > Speed factor 53.4
    | > | >
    | > | > **Memory Bandwidth**
    | > | > Int. Buffered 6042
    | > | > Float Buffered 6021
    | > | > Est. Efficiency 63%
    | > | > __________
    | > | > Memory bus = 1200 MHz
    | > | >
    | > | > **Memory Latency**
    | > | > Random 16 MByte 63.5 ns / 171.3 clocks
    | > | > Linear 16 MByte 9.3 ns / 25.4 clocks
    | > | >
    | > | > **Cache and Memory**
    | > | > Combined Index 19725
    | > | > Speed Factor 36.9
    | > | >
    | > | > **Memory Bandwidth**
    | > | > Int. Buffered: 6438
    | > | > Float Buffered 6442
    | > | > Est. Efficiency 67%
    | > | > __________
    | > | >
    | > | > Hope this helps.
    | > | >
    | > | > Phil Weldon
    | > | >
    | > | >
    | > |
    | > |
    | >
    | >
    |
    |
     
    Phil Weldon, Apr 24, 2007
    #15
  16. Phil,
    I am not at home this afternoon, and won't be this evening either. From what
    I remember, but I may be wrong, tCMD = 4 would be equal to you saying CMD =
    4T. The CMD latency is 4 clock periods in other words. I did not try to
    change this value, as it apparently depends on the mobo chipset.
    The PC2-5300 mem I use is DDR2 667, which means memory internal clock = 166
    MHz, memory I/O bus clock = 333 MHz and bus transfer rate = 667 MHz. All
    this measured for one 8 bit wide mem chip. As there are 8 chips per mem
    module (64 bits wide bus), the last number must be multiplied by 8 to get
    the bandwidth in MB/sec, hence the PC2-5300.
    Our mutual misunderstanding comes from the fact that the CPU : mem ratio
    coming from the Crucial web site and from CPU-Z define the ratio as CPU
    input clock : mem I/O bus clock. You use CPU input clock : mem internal
    clock.
    As the I/O bus mem clock is twice the internal mem clock......
    So, in my case, CPU-Z reports a 1 : 1 ratio, and by you a 1 : 2 ratio.
    Now, which one is the most effective, the speediest?
    Should I run and buy DDR2 1333 (PC2-10600) mem modules, or would the gain in
    actual bandwidth be ridiculous when compared to the price difference?
    And what about any speed gain in real mem intensive applications?

    Michka

     
    M. R. Carleer, Apr 24, 2007
    #16
  17. Phil Weldon

    Paul Guest

    This document you can download from the Corsair site, talks about
    their attempts to add additional byte values to the SPD chip on the
    DIMM. This EPP function is intended to better support "performance"
    memory. But I don't get the association with "SLI memory", so it
    must be some clever marketing terms.

    http://corsairmemory.com/corsair/products/specs/EPP_Specification_v01.pdf

    I just checked, and there is also an entry here on the subject. I
    guess working "SLI" into the marketing terms, helps sell video cards
    or something.

    http://en.wikipedia.org/wiki/Enhanced_Performance_Profiles

    Paul
     
    Paul, Apr 24, 2007
    #17
  18. From what I read, it seems that SLI-ready and EPP are one and the same
    thing.
    Basically, the JEDEC wrote a standard about what should be written in the
    SPD module about the parameters of the mem.
    However, a lot of free space was still available in the SPD EEPROM chip.
    nVidia and Corsair came up with additional pieces of info in order to ease
    overclocking. This addition was called Enhanced Parameters Profiles (EPP)
    and/or SLI-ready as named by nVidia. Nothing to do with the use of 2 video
    cards as I understand, only marketing.

    Michka
     
    Michel R. Carleer, Apr 24, 2007
    #18
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