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Writing 9 bits in a sequence to perform Soft Reset

Discussion in 'Embedded' started by ssubbarayan, Apr 17, 2007.

  1. ssubbarayan

    ssubbarayan Guest

    Hi all,
    This is again a follow up on EEPROM discussion I had previously a few
    days back.Regarding I2C based EEPROM I recently came across an
    application note from Microchip company (Document name AN709).
    The note says :

    In all designs it is recommended that a software reset sequence be
    sent to the EEPROM as part of the microcontrollers power up sequence.
    This sequence guarantees that the EEPROM is in a correct and known
    Assuming that the EEPROM has powered up into an incorrect state (or
    that a reset occurred at the microcontroller during communication),
    the following sequence (which is further explained below) should be
    sent in order to guarantee that the serial EEPROM device is properly
    · START Bit
    · Clock in nine bits of '1'
    · START Bit
    · STOP Bit
    The first START bit will cause the device to reset from a state in
    which it is expecting to receive data from the microcontroller. In
    this mode the device is monitoring the data bus in receive mode and
    can detect the START bit which forces an internal reset. The nine bits
    of '1' are used to force a reset of those devices that could not be
    reset by the previous START bit. This occurs only if the device is in
    a mode where it is either driving an acknowledge on the bus (low), or
    is in
    an output mode and is driving a data bit of '0' out on the bus. In
    both of these cases the previous START bit (defined as SDA going low
    while SCL is high) could not be generated due to the device holding
    the bus low. By sending nine bits of '1' it is guaranteed that the
    device will see a NACK (microcontroller does not drive the bus low to
    acknowledge data sent by EEPROM) which also
    forces an internal reset.
    The second START bit is sent to guard against the rare possibility of
    an erroneous write that could occur if the microcontroller was reset
    while sending a write command to the EEPROM, and, the EEPROM was
    driving an ACK on the bus when the first START bit was sent. In
    this special case if this second START bit was not sent, and instead
    the STOP bit was sent, the device could initiate a write cycle. This
    potential for an erroneous write occurs only in the event of the
    microcontroller being reset while sending a write command to the
    EEPROM. The final STOP bit terminates bus activity and puts the EEPROM
    in standby mode.
    This sequence does not effect any other I2C devices which may be on
    the bus as they will simply disregard it as an invalid command".
    I believe this should be done in our software as a protection
    mechanism.The above APPNOTE says its applicable to all I2C EEPROM
    My queries are:

    1)If I have understood correctly,I need to send a startbit and a
    sequence of 9 bits to my EEPROM device.Here comes the problem:
    How will I be able to send 9 bits when my NVRAM chip(mb24256) can
    allow to write only 8 bits per time?
    I use 5516 ST chip and this chip acts as I2C master and the above
    mentioned (mb24256) EEPROM chip acts as a slave device.

    Have any of you come across such a situation?How to overcome this
    problem?Is it feasible for my chip?

    Sorry for a long description,but believe this is clear to all to
    understand the problem.
    Advanced thanks for all your replys and looking farward for the same,

    ssubbarayan, Apr 17, 2007
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